The paper presents a quantization-theoretic framework for studying incremental Σ∆ quantization systems. The framework makes it possible to efficiently compute the quantization intervals and hence the transfer function of the quantizer, and to determine the mean square error (MSE) and maximum error for the optimal and conventional linear filters for first and second order incremental Σ∆ modulators. The results show that the optimal filter can significantly outperform conventional linear filters in terms of both MSE and maximum error. The performance of conventional Σ∆ quantizers is then compared to that of incremental Σ∆ with optimal filtering for bandlimited signals. It is shown that incremental Σ∆ can outperform the conventional approach in terms of signal to noise+distortion ratio (SNDR) and the characteristics of the power spectral density (PSD). The framework is also used to provide a simpler and more intuitive derivation of the Zoomer algorithm.

The paper investigates the suitability of Σ ∆ modulation based FPA readout schemes for use in Vertically Interconnected Sensor Arrays requiring ultra high dynamic range and frame rate. It is shown that the extended counting scheme is capable of achieving the DR and frame rate requirements but at the expense of high power consumption. Extended counting is also shown to outperform several other HDR schemes in terms of SNR at the ultra high DR and frame rate.

Abstract — The stringent performance requirements of many infrared imaging applications warrant the development of precision high dynamic range, high speed focal plane arrays. In addition to achieving high dynamic range, the readout circuits for these image sensors must achieve high linearity and SNR at low power consumption. We first review two high dynamic range image sensor schemes that have been developed for visible range imaging and discuss why they cannot meet the stringent performance demands of infrared imaging. We then describe a new dynamic range extension scheme, Folded Multiple Capture, that can meet these performance requirements. Dynamic range is extended using synchronous self-reset while high SNR is maintained using few non-uniformly spaced captures and leastsquares fit to estimate pixel photocurrent. We conclude with a description of a prototype of this architecture targeted for 3D-IC IR focal plane arrays. I.

Earlier studies have shown that multiple capture can achieve high SNR, but cannot satisfy the high dynamic range (HDR) and high speed requirements of the Vertically-Integrated-Sensor-Array (VISA) project. Synchronous selfreset, on the other hand, can achieve these requirements, but suffers from poor SNR. Extended counting can achieve high dynamic range at high frame rate and with good SNR, but at the expense of high power consumption. The paper proposes a new HDR focal plane array architecture, denoted by folded-multiple capture (FMC), which by combining features of the synchronous self-reset and multiple capture schemes, can satisfy the VISA requirements at a fraction of the power dissipation and with more robustness to device variations than extended counting. The architecture is also capable of detecting subframe disturbances, e.g., due to laser jamming, and correcting for it.

Abstract — Area and power optimization of a first-order deltasigma analog-to-digital converter (ADC) for pixel-level data conversion is presented. The ADC is designed for use in a verticallyintegrated logarithmic CMOS image sensor. A switched-capacitor modulator with minimum area has been employed. Unlike other similar structures, the decimation is performed inside the pixel to decrease its output bit rate. The proposed ADC has an area of 32 × 31 µm 2 and consumes 680 nW of power to achieve 80 dB of signal-to-noise ratio with a frame rate of 50 Hz. The circuit was implemented in 0.18 µm CMOS technology with a die area of 2mm 2 and has been sent for fabrication. I.

The market for solid-state image sensors has been experiencing explosive growth in recent years due to the increasing demands of mobile imaging, digital still and video cameras, Internet-based video conferencing, surveillance, and biometrics. With over 230 million parts shipped in 2004 and an estimated annual growth rate of over 28 % (In-Stat/MDR), image sensors have become a significant silicon technology driver. Charge-coupled devices (CCDs) have traditionally been the dominant image-sensor technology. Recent advances in the design of image sensors implemented in complementary metaloxide semiconductor (CMOS) technologies have led to their adoption in several high-volume products, such as the optical mouse, PC cameras, mobile phones, and high-end digital cameras, making them a viable alternative to CCDs. Additionally, by exploiting the ability to integrate sensing with analog and digital processing down to the pixel level, new types of CMOS imaging devices are being created for manmachine interface, surveillance and monitoring, machine vision, and biological testing, among other applications. In this article, we provide a basic introduction to CMOS image-sensor technology, design, and performance limits and present recent

Abstract — A prototype of a new high dynamic range readout scheme targeted for 3D-IC IR focal plane arrays is described. Dynamic range is extended using synchronous self-reset while high SNR is maintained using few non-uniformly spaced captures and least-squares fit to estimate pixel photocurrent. The prototype comprises of a 16×5 readout pixel array fabricated in a 0.18µm CMOS process and achieves 138dB dynamic range and 60dB peak SNR at 1000 frames/sec with energy consumption of 25.5nJ per pixel readout. I.