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Optimal Wire and Transistor Sizing for Circuits with NonTree Topology
, 1997
"... Conventional methods for optimal sizing of wires and transistors use linear RC circuit models and the Elmore delay as a measure of signal delay. If the RC circuit has a tree topology the sizing problem reduces to a convex optimization problem which can be solved using geometric programming. The tree ..."
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Cited by 26 (8 self)
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Conventional methods for optimal sizing of wires and transistors use linear RC circuit models and the Elmore delay as a measure of signal delay. If the RC circuit has a tree topology the sizing problem reduces to a convex optimization problem which can be solved using geometric programming. The tree topology restriction precludes the use of these methods in several sizing problems of significant importance to highperformance deep submicron design including, for example, circuits with loops of resistors, e.g., clock distribution meshes, and circuits with coupling capacitors, e.g., buses with crosstalk between the lines. The paper proposes a new optimization method which can be used to address these problems. The method uses the dominant time constant as a measure of signal propagation delay in an RC circuit, instead of Elmore delay. Using this measure, sizing of any RC circuit can be cast as a convex optimization problem which can be solved using the recently developed efficient interiorpoint methods for semidefinite programming. The method is applied to two important sizing problems sizing of clock meshes, and sizing of buses in the presence of crosstalk.
Analytical Delay Models for VLSI Interconnects Under Ramp Input
 IEEE ICCAD
, 1996
"... Elmore delay has been widely used as an analytical estimate of interconnect delays in the performancedriven synthesis and layout of VLSI routing topologies. However,for typical RLC interconnectionswith ramp input, Elmore delay can deviate by up to 100 % or more from SPICEcomputed delay since it is ..."
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Cited by 25 (7 self)
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Elmore delay has been widely used as an analytical estimate of interconnect delays in the performancedriven synthesis and layout of VLSI routing topologies. However,for typical RLC interconnectionswith ramp input, Elmore delay can deviate by up to 100 % or more from SPICEcomputed delay since it is independent of rise time of the input ramp signal. We develop new analytical delay models based on the first and second moments of the interconnect transfer function when the input is a ramp signal with finite rise time. Delay estimates using our first moment based analytical models are within 4 % of SPICEcomputed delay, and models based on both first and second moments are within 2:3 % of SPICE, across a wide range of interconnect parameter values. Evaluation of our analytical models is several orders of magnitude faster than simulation using SPICE. We also describe extensions of our approach for estimation of sourcesink delays in arbitrary interconnect trees.
Optimizing dominant time constant in RC circuits
, 1996
"... We propose to use the dominant time constant of a resistorcapacitor (RC) circuit as a measure of the signal propagation delay through the circuit. We show that the dominant time constant is a quasiconvex function of the conductances and capacitances, and use this property to cast several interestin ..."
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Cited by 16 (7 self)
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We propose to use the dominant time constant of a resistorcapacitor (RC) circuit as a measure of the signal propagation delay through the circuit. We show that the dominant time constant is a quasiconvex function of the conductances and capacitances, and use this property to cast several interesting design problems as convex optimization problems, specifically, semidefinite programs (SDPs). For example, assuming that the conductances and capacitances are affine functions of the design parameters (which is a common model in transistor or interconnect wire sizing), one can minimize the power consumption or the area subject to an upper bound on the dominant time constant, or compute the optimal tradeoff surface between power, dominant time constant, and area. We will also note that, to a certain extent, convex optimization can be used to design the topology of the interconnect wires. This approach has two advantages over methods based on Elmore delay optimization. First, it handles a far wider class of circuits, e.g., those with nongrounded capacitors. Second, it always results in convex optimization problems for which very efficient interiorpoint methods have recently been developed. We illustrate the method, and extensions, with several examples involving optimal wire and transistor sizing.
A Reduction Technique for RLCG Interconnects Using Least Squares Method
"... The analysis and design of high speed LSI chips are becoming more and more important, because the subcircuits coupled with interconnects embedded in the substrate sometimes cause the fault switching operations due to the signal ..."
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The analysis and design of high speed LSI chips are becoming more and more important, because the subcircuits coupled with interconnects embedded in the substrate sometimes cause the fault switching operations due to the signal
Interconnect Modeling Using Numerical Inversion of Laplace Transforms
"... In this paper, the admittance matrix of RLCG interconnects is modeled by partial fractions composed of the exact poles of the admittance matrix and the corresponding residues. The exact poles can be obtained by applying the LeverrierFaddeeva algorithm. In this paper, a new method for calculating t ..."
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In this paper, the admittance matrix of RLCG interconnects is modeled by partial fractions composed of the exact poles of the admittance matrix and the corresponding residues. The exact poles can be obtained by applying the LeverrierFaddeeva algorithm. In this paper, a new method for calculating the residues is proposed. The residues can be calculated by using numerical inversion of Laplace transforms and the least squares method so that the impulse or pulse response of the partial fraction is matched with the one of each element of the exact admittance matrix in the timedomain. From the partial fraction representation, asymptotic equivalent circuit models suitable for SPICElike simulators can be synthesized. 1.
352 IEEE TRANSACTIONS ON COMPUTERAIDED DESIGN. VOL. 9. NO. 4. APRIL I990 Asymptotic Waveform Evaluation for Timing Analysis
"... AbstractFor digital system designs the propagation delays due to the physical interconnect can have a significant, even dominant, impact on performance. Timing analyzers attempt to capture the effect of the interconnect on the delay with a simplified model, typically an RC tree. For midfrequency M ..."
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AbstractFor digital system designs the propagation delays due to the physical interconnect can have a significant, even dominant, impact on performance. Timing analyzers attempt to capture the effect of the interconnect on the delay with a simplified model, typically an RC tree. For midfrequency MOS integrated circuits the RC tree methods can predict the delay to within 10 percent of a SPICE simulation and at faster than lOOOx the speed. With continual progress in integrated circuit processing, operating speeds and new technologies are emerging that may require more elaborate interconnect models. Digital bipolar and highspeed MOS integrated systems can require interconnect models which contain coupling capacitors and inductors. In addition, to enable timing verification at the printed circuit hoard level also requires general RLC interconnect models. Asymptotic Waveform Evaluation (AWE) provides a generalized approach to linear RLC circuit response approximations. The RLC interconnect model may contain floating capacitors, grounded resistors, inductors, and even linear controlled sources. The transient portion of the response is approximated by matching the initial boundary conditions and the first 2q1 moments of the exact response to a lower order qpole model. For the case of an RC tree model a firstorder AWE approximation reduces to the RC tree methods. I.
Automation Conf., 1971, pp. 155169.
, 1981
"... A. Hashimoto and J. Stevens, “Wire routing by optimizing channel ..."
HIGHLIGHTS IN PHYSICAL SIMULATION AND ANALYSIS AT ICCAD
"... Six papers were chosen to represent twenty years of research in physical simulation and analysis, three papers addressing the problem of extracting and simulating interconnect effects and three papers describing techniques for simulating steadystate and noise behavior in RF circuits. In this commen ..."
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Six papers were chosen to represent twenty years of research in physical simulation and analysis, three papers addressing the problem of extracting and simulating interconnect effects and three papers describing techniques for simulating steadystate and noise behavior in RF circuits. In this commentary paper we will try to describe the contribution of each paper and place that contribution in some historical context.