Conventional methods for optimal sizing of wires and transistors use linear RC circuit models and the Elmore delay as a measure of signal delay. If the RC circuit has a tree topology the sizing problem reduces to a convex optimization problem which can be solved using geometric programming. The tree topology restriction precludes the use of these methods in several sizing problems of significant importance to high-performance deep submicron design including, for example, circuits with loops of resistors, e.g., clock distribution meshes, and circuits with coupling capacitors, e.g., buses with crosstalk between the lines. The paper proposes a new optimization method which can be used to address these problems. The method uses the dominant time constant as a measure of signal propagation delay in an RC circuit, instead of Elmore delay. Using this measure, sizing of any RC circuit can be cast as a convex optimization problem which can be solved using the recently developed efficient interi...

Elmore delay has been widely used as an analytical estimate of interconnect delays in the performance-driven synthesis and layout of VLSI routing topologies. However,for typical RLC interconnectionswith ramp input, Elmore delay can deviate by up to 100 % or more from SPICEcomputed delay since it is independent of rise time of the input ramp signal. We develop new analytical delay models based on the first and second moments of the interconnect transfer function when the input is a ramp signal with finite rise time. Delay estimates using our first moment based analytical models are within 4 % of SPICE-computed delay, and models based on both first and second moments are within 2:3 % of SPICE, across a wide range of interconnect parameter values. Evaluation of our analytical models is several orders of magnitude faster than simulation using SPICE. We also describe extensions of our approach for estimation of source-sink delays in arbitrary interconnect trees.

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We propose to use the dominant time constant of a resistor-capacitor (RC) circuit as a measure of the signal propagation delay through the circuit. We show that the dominant time constant is a quasiconvex function of the conductances and capacitances, and use this property to cast several interesting design problems as convex optimization problems, specifically, semidefinite programs (SDPs). For example, assuming that the conductances and capacitances are affine functions of the design parameters (which is a common model in transistor or interconnect wire sizing), one can minimize the power consumption or the area subject to an upper bound on the dominant time constant, or compute the optimal tradeoff surface between power, dominant time constant, and area. We will also note that, to a certain extent, convex optimization can be used to design the topology of the interconnect wires. This approach has two advantages over methods based on Elmore delay optimization. First, it handles a far wider class of circuits, e.g., those with non-grounded capacitors. Second, it always results in convex optimization problems for which very efficient interiorpoint methods have recently been developed. We illustrate the method, and extensions, with several examples involving optimal wire and transistor sizing.

Conventional methods for optimal sizing of wires and transistors use linear RC circuit models and the Elmore delay as a measure of signal delay. If the RC circuit has a tree topology the sizing problem reduces to a convex optimization problem which can be solved using geometric programming. The tree topology restriction precludes the use of these methods in several sizing problems of significant importance to highperformance deep submicron design including, for example, circuits with loops of resistors, e.g., clock distribution meshes, and circuits with coupling capacitors, e.g., buses with crosstalk between the lines. The paper proposes a new optimization method which can be used to address these problems. The method uses the dominant time constant as a measure of signal propagation delay in an RC circuit, instead of Elmore delay. Using this measure, sizing of any RC circuit can be cast as a convex optimization problem which can be solved using the recently developed efficient interior-point methods for semidefinite programming. The method is applied to two important sizing problems- sizing of clock meshes, and sizing of buses in the presence of crosstalk. 1