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Pattern Independent Maximum Current Estimation in Power and Ground Buses of CMOS VLSI Circuits: Algorithms, Signal Correlations and Their Resolution
 IEEE Transactions on ComputerAided Design
, 1995
"... Currents flowing in the power and ground (P&G) buses of CMOS digital circuits affect both circuit reliability and performance by causing excessive voltage drops. Excessive voltage drops manifest themselves as glitches on the P&G buses and cause erroneous logic signals and degradation in swit ..."
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Cited by 48 (8 self)
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Currents flowing in the power and ground (P&G) buses of CMOS digital circuits affect both circuit reliability and performance by causing excessive voltage drops. Excessive voltage drops manifest themselves as glitches on the P&G buses and cause erroneous logic signals and degradation in switching speeds. Maximum current estimates are needed at every contact point in the buses to study the severity of the voltage drop problems and to redesign the supply lines accordingly. These currents, however, depend on the specific input patterns that are applied to the circuit. Since it is prohibitively expensive to enumerate all possible input patterns, this problem has, for a long time, remained largely unsolved. In this paper, we propose a patternindependent, linear time algorithm (iMax) that estimates at every contact point, an upper bound envelope of all possible current waveforms that result by the application of different input patterns to the circuit. The algorithm is extremely efficient an...
Optimizing dominant time constant in RC circuits
, 1996
"... We propose to use the dominant time constant of a resistorcapacitor (RC) circuit as a measure of the signal propagation delay through the circuit. We show that the dominant time constant is a quasiconvex function of the conductances and capacitances, and use this property to cast several interestin ..."
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Cited by 16 (7 self)
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We propose to use the dominant time constant of a resistorcapacitor (RC) circuit as a measure of the signal propagation delay through the circuit. We show that the dominant time constant is a quasiconvex function of the conductances and capacitances, and use this property to cast several interesting design problems as convex optimization problems, specifically, semidefinite programs (SDPs). For example, assuming that the conductances and capacitances are affine functions of the design parameters (which is a common model in transistor or interconnect wire sizing), one can minimize the power consumption or the area subject to an upper bound on the dominant time constant, or compute the optimal tradeoff surface between power, dominant time constant, and area. We will also note that, to a certain extent, convex optimization can be used to design the topology of the interconnect wires. This approach has two advantages over methods based on Elmore delay optimization. First, it handles a far wider class of circuits, e.g., those with nongrounded capacitors. Second, it always results in convex optimization problems for which very efficient interiorpoint methods have recently been developed. We illustrate the method, and extensions, with several examples involving optimal wire and transistor sizing.
On HighSpeed VLSI Interconnects: Analysis and Design
 Proc. AsiaPacific Conf. on Circuits and Systems
, 1992
"... We survey our recent work in the analysis and design of interconnect topologies for highspeed VLSI. Results include: a new, fast distributed RLC analysis method based on a twopole approximation; an Atree formulation for performancedriven interconnect; an optimal wiresizing algorithm; and new cri ..."
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Cited by 12 (8 self)
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We survey our recent work in the analysis and design of interconnect topologies for highspeed VLSI. Results include: a new, fast distributed RLC analysis method based on a twopole approximation; an Atree formulation for performancedriven interconnect; an optimal wiresizing algorithm; and new criticalpath dependent routing tree algorithms. 1 Introduction Interconnection design is becoming a major concern in the design of highspeed systems, where stateoftheart integrated circuits use submicron technology and operate at multigiga hertz clock rates. In this range, optimization based on the traditional layout design objective, i.e. minimization of chip area, no longer suffices since the emphasis on system performance requires different consideration. For instance, the minimum Steiner tree has traditionally been the preferred interconnect topology because: (1) it uses the minimum wiring area and (2) minimum wiring area results in minimum wire capacitance, which is the dominant fac...
BEHAVIORAL MODEL OF SYMMETRICAL MULTI LEVEL TTREE INTERCONNECTS
"... Abstract—An accurate and behavioral modeling method of symmetrical Ttree interconnect network is successfully investigated in this paper. The Ttree network topology understudy is consisted of elementary lumped Lcells formed by series impedance and parallel admittance. It is demonstrated how th ..."
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Cited by 1 (1 self)
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Abstract—An accurate and behavioral modeling method of symmetrical Ttree interconnect network is successfully investigated in this paper. The Ttree network topology understudy is consisted of elementary lumped Lcells formed by series impedance and parallel admittance. It is demonstrated how the inputoutput signal paths of this single input multiple output (SIMO) tree network can be reduced to single input single output (SISO) network composed of Lcells in cascade. The literal expressions of the currents, the input impedances and the voltage transfer function of the Ttree electrical interconnect via elementary transfer matrix products are determined. Thus, the exact expression of the multilevel behavioral Ttree transfer function is established. The routine algorithm developed was implemented in Matlab programs. As application of the developed modeling method, the analysis of Ttree topology comprised of different and identical RLCcells is conducted. To demonstrate the relevance of the model established, lumped RLC Ttree networks with different levels for the microelectronic interconnect application are designed and simulated. The work flow illustrating the guideline for the application of the routine algorithm summarizing the modeling method is proposed. Then, 3Dmicrostrip Ttree interconnects with width 0.1µm and length 3mm printed on FR4substrate were considered. As results, a very good agreement between the results from the reduced behavioral model proposed and SPICEcomputations is found both in frequency and timedomains by considering arbitrary binary sequence “01001100 ” with 2Gsym/s rate. The model proposed in this paper presents significant benefits in terms of flexibility and very less computation times. It can be used during the design process of the PCB and the microelectronic circuits for the signal integrity prediction. In the continuation of this
NONTREE REDUCTION TO CALCULATE SECOND ORDER DELAY
"... The computation of second order delay for nontree circuits has been necessitated by the thirst for accuracy in estimation of delay and also the increasing use of nontree type circuits in modern chip design. The calculation of first order moments in tree type circuits is straightforward and can be ..."
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The computation of second order delay for nontree circuits has been necessitated by the thirst for accuracy in estimation of delay and also the increasing use of nontree type circuits in modern chip design. The calculation of first order moments in tree type circuits is straightforward and can be repeated iteratively to obtain higher order moments. The objective is to develop a closedformula to convert a nontree circuit to tree circuit so that it will be easier to obtain second order delay. The reduction technique is based on moment matching. Partial results have been obtained and are described in the later sections. PSPICE simulations were carried out to validate the obtained results.
Automation Conf., 1971, pp. 155169.
, 1981
"... A. Hashimoto and J. Stevens, “Wire routing by optimizing channel ..."