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The Elmore Delay as a Bound for RC Trees with Generalized Input Signals
 the IEEE Transactions on CAD. (Available
"... The Elmore delay is an extremely popular delay metric, particularly for RC tree analysis. The widespread usage of this metric is mainly attributable to it being the most accurate delay measure that is a simple analytical function of the circuit parameters. The only drawbacks to this delay metric are ..."
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Cited by 38 (0 self)
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The Elmore delay is an extremely popular delay metric, particularly for RC tree analysis. The widespread usage of this metric is mainly attributable to it being the most accurate delay measure that is a simple analytical function of the circuit parameters. The only drawbacks to this delay metric are the uncertainty as to whether it is an optimistic or a pessimistic estimate, and the restriction to step response delay estimation. In this paper, we prove that the Elmore delay is an absolute upper bound on the 50 % delay of an RC tree response. Moreover, we prove that this bound holds for input signals other than steps, and that the actual delay asymptotically approaches the Elmore delay as the input signal rise time increases. A lower bound on the delay is also developed using the Elmore delay and the second moment of the impulse response. The utility of this bound is for understanding the accuracy and the limitations of the Elmore delay metric as we use it for design automation. I.
Computing signal delay in general RC networks by tree/link partitioning
 IEEE Transactions on ComputerAided Design
, 1990
"... S. Patel and J. Patel, “Effectiveness of heuristics for automatic test ..."
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Cited by 29 (0 self)
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S. Patel and J. Patel, “Effectiveness of heuristics for automatic test
Optimal Wire and Transistor Sizing for Circuits with NonTree Topology
 in Proc. Int. Conf. on Computer Aided Design
, 1997
"... Conventional methods for optimal sizing of wires and transistors use linear RC circuit models and the Elmore delay as a measure of signal delay. If the RC circuit has a tree topology the sizing problem reduces to a convex optimization problem which can be solved using geometric programming. The tree ..."
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Cited by 28 (11 self)
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Conventional methods for optimal sizing of wires and transistors use linear RC circuit models and the Elmore delay as a measure of signal delay. If the RC circuit has a tree topology the sizing problem reduces to a convex optimization problem which can be solved using geometric programming. The tree topology restriction precludes the use of these methods in several sizing problems of significant importance to highperformance deep submicron design including, for example, circuits with loops of resistors, e.g., clock distribution meshes, and circuits with coupling capacitors, e.g., buses with crosstalk between the lines. The paper proposes a new optimization method which can be used to address these problems. The method uses the dominant time constant as a measure of signal propagation delay in an RC circuit, instead of Elmore delay. Using this measure, sizing of any RC circuit can be cast as a convex optimization problem which can be solved using the recently developed efficient interi...
Optimizing dominant time constant in RC circuits
, 1996
"... We propose to use the dominant time constant of a resistorcapacitor (RC) circuit as a measure of the signal propagation delay through the circuit. We show that the dominant time constant is a quasiconvex function of the conductances and capacitances, and use this property to cast several interestin ..."
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Cited by 16 (8 self)
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We propose to use the dominant time constant of a resistorcapacitor (RC) circuit as a measure of the signal propagation delay through the circuit. We show that the dominant time constant is a quasiconvex function of the conductances and capacitances, and use this property to cast several interesting design problems as convex optimization problems, specifically, semidefinite programs (SDPs). For example, assuming that the conductances and capacitances are affine functions of the design parameters (which is a common model in transistor or interconnect wire sizing), one can minimize the power consumption or the area subject to an upper bound on the dominant time constant, or compute the optimal tradeoff surface between power, dominant time constant, and area. We will also note that, to a certain extent, convex optimization can be used to design the topology of the interconnect wires. This approach has two advantages over methods based on Elmore delay optimization. First, it handles a far wider class of circuits, e.g., those with nongrounded capacitors. Second, it always results in convex optimization problems for which very efficient interiorpoint methods have recently been developed. We illustrate the method, and extensions, with several examples involving optimal wire and transistor sizing.
A General Approach to Performance Analysis and Optimization of Asynchronous Circuits
, 1995
"... A systematic approach for evaluating and optimizing the performance of asynchronous VLSI circuits is presented. Indexpriority simulation is introduced to efficiently find minimal cycles in the state graph of a given circuit. These minimal cycles are used to determine the causality relationships bet ..."
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Cited by 14 (0 self)
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A systematic approach for evaluating and optimizing the performance of asynchronous VLSI circuits is presented. Indexpriority simulation is introduced to efficiently find minimal cycles in the state graph of a given circuit. These minimal cycles are used to determine the causality relationships between all signal transitions in the circuit. Once these relationships are known, the circuit is then modeled as an extended eventrule system, which can be used to describe many circuits, including ones that are inherently disjunctive. An accurate indication of the performance of the circuit is obtained by analytically computing the period of the corresponding extended eventrule system.
Timing optimization for multisource nets: characterization and optimal repeater insertion
 IEEE TRANSATIONS ON COMPUTER AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
, 1999
"... This paper presents new results in the area of timing optimization for multisource nets. The augmented RCdiameter (ARD) is suggested as a natural and practical performance measure and a linear time algorithm for computing the ARD of a multisource net is presented. Building on the ARD measure, we ch ..."
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Cited by 10 (1 self)
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This paper presents new results in the area of timing optimization for multisource nets. The augmented RCdiameter (ARD) is suggested as a natural and practical performance measure and a linear time algorithm for computing the ARD of a multisource net is presented. Building on the ARD measure, we characterize the multisource optimization problem in terms of operations on piecewise linear functions. This characterization is then used to develop an algorithm for optimal repeater insertion: for a given multisource topology the algorithm efficiently identifies an optimal assignment of repeaters to prescribed insertion points under the “min cost timing feasible” problem formulation. The algorithm has been implemented and computational results demonstrate the viability of the approach.
Robust Elmore Delay Models Suitable for Full Chip Timing Verification of a 600MHz CMOS Microprocessor
 In Proceedings of ACM/IEEE Design Automation Conference
, 1998
"... In this paper we introduce a method for computing the Elmore delay of MOS circuits which relies on a model of the capacitance of MOS devices and a model of the Elmore delay of individual MOS devices. The resistance of a device is not explicitly modelled. The Elmore models are used to compute the Elm ..."
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Cited by 5 (0 self)
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In this paper we introduce a method for computing the Elmore delay of MOS circuits which relies on a model of the capacitance of MOS devices and a model of the Elmore delay of individual MOS devices. The resistance of a device is not explicitly modelled. The Elmore models are used to compute the Elmore delay and the 50# point delay of CMOS circuits in a static timing verifier. Elmore delays computed with these models fall within 10# of SPICE and can be computed thousands of times faster than if computed using SPICE. These models were used to verify critical paths during the design of a 600MHz microprocessor.
A sumoverpaths impulseresponse momentextraction algorithm for ICinterconnect networks: verification, coupled
 RC Lines,” in Proc. ICCAD
, 2003
"... We have created a stochastic impulseresponse (IR) momentextraction algorithm for RC circuit networks. It employs a newly discovered Feynman SumoverPaths Postulate. Full parallelism has been preserved. Numerical verification results for coupled RC lines confirmed rapid convergence. We believe this ..."
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Cited by 2 (0 self)
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We have created a stochastic impulseresponse (IR) momentextraction algorithm for RC circuit networks. It employs a newly discovered Feynman SumoverPaths Postulate. Full parallelism has been preserved. Numerical verification results for coupled RC lines confirmed rapid convergence. We believe this algorithm may find useful application in massively coupled electrical systems, such as those encountered in highend digitalIC interconnects. Categories and Subject Descriptors [Verification, Modeling and Simulation]: 3.1 Interconnectparameter extraction and circuitmodel generation. 3.2 Signalintegrity analysis. Power/Ground network analysis.
Architecture and Implementations for Polynomial Ring Engine Over Small Residue Rings
, 1997
"... stored or otherwise retained in a retrieval system or transmitted in any form, on any medium or by any means without the prior written ..."
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Cited by 1 (0 self)
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stored or otherwise retained in a retrieval system or transmitted in any form, on any medium or by any means without the prior written