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Activefeedback frequencycompensation technique for lowpower multistage amplifiers
 IEEE J. SolidState Circuits
, 2003
"... technique for lowpower operational amplifiers is presented in this paper. With an activefeedback mechanism, a highspeed block separates the lowfrequency highgain path and highfrequency signal path such that high gain and wide bandwidth can be achieved simultaneously in the AFFC amplifier. The ..."
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technique for lowpower operational amplifiers is presented in this paper. With an activefeedback mechanism, a highspeed block separates the lowfrequency highgain path and highfrequency signal path such that high gain and wide bandwidth can be achieved simultaneously in the AFFC amplifier. The gain stage in the activefeedback network also reduces the size of the compensation capacitors such that the overall chip area of the amplifier becomes smaller and the slew rate is improved. Furthermore, the presence of a lefthalfplane zero in the proposed AFFC topology improves the stability and settling behavior of the amplifier. Threestage amplifiers based on AFFC and nestedMiller compensation (NMC) techniques have been implemented by a commercial 0.8 m CMOS process. When driving a 120pF capacitive load, the AFFC amplifier achieves over 100dB dc gain, 4.5MHz gainbandwidth product (GBW) , 65 phase margin, and 1.5V / s average slew rate, while only dissipating 400 W power at a 2V supply. Compared to a threestage NMC amplifier, the proposed AFFC amplifier provides improvement in both the GBW and slew rate by 11 times and reduces the chip area by 2.3 times without significant increase in the power consumption. Index Terms—Active feedback, activecapacitivefeedback network, amplifiers, frequency compensation, multistage amplifiers.
Automatic synthesis of operational amplifiers based on analytic circuit models
 Proceedings of IEEE International Conference on ComputerAided Design
, 1987
"... An automatic synthesis tool for CMOS op amps (OPASYN) has been developed. The program starts from one of a number of op amp circuits and proceeds to optimize various device sizes and bias currents to meet a given set of design specifications. Because it uses analytic circuit models in its inner opti ..."
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An automatic synthesis tool for CMOS op amps (OPASYN) has been developed. The program starts from one of a number of op amp circuits and proceeds to optimize various device sizes and bias currents to meet a given set of design specifications. Because it uses analytic circuit models in its inner optimization loop, it can search efficiently through a large part of the possible solution space. The program has a SPICE interface that automatically performs circuit simulations for the candidate solutions to verify the results of the synthesis and optimization procedure. The simulation results are also used to finetune the analytic circuit descriptions in the database. OPASYN has been implemented in Franz Lisp and demonstrated for three different basic circuits with a conventional 3 µm process and a more advanced 1.5 µm process. Experiments have shown that OPASYN quickly produces practical designs which will meet reasonable design objectives. 1.
A TransientEnhanced LowQuiescent Current LowDropout Regulator With Buffer Impedance Attenuation
"... Abstract—This paper presents a lowdropout regulator (LDO) for portable applications with an impedanceattenuated buffer for driving the pass device. Dynamicallybiased shunt feedback is proposed in the buffer to lower its output resistance such that the pole at the gate of the pass device is pushed ..."
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Abstract—This paper presents a lowdropout regulator (LDO) for portable applications with an impedanceattenuated buffer for driving the pass device. Dynamicallybiased shunt feedback is proposed in the buffer to lower its output resistance such that the pole at the gate of the pass device is pushed to high frequencies without dissipating large quiescent current. By employing the currentbuffer compensation, only a single pole is realized within the regulation loop unitygain bandwidth and over 65 phase margin is achieved under the full range of the load current in the LDO. The LDO thus achieves stability without using any lowfrequency zero. The maximum outputvoltage variation can be minimized during load transients even if a small output capacitor is used. The LDO with the proposed impedanceattenuated buffer has been implemented in a 0.35 m twinwell CMOS process. The proposed LDO dissipates 20 A quiescent current at noload condition and is able to deliver up to 200mA load current. With a1F output capacitor, the maximum transient outputvoltage variation is within 3 % of the output voltage with load step changes of 200 mA/100 ns. Index Terms—Linear regulator, load transient response, lowdropout regulator (LDO), pass device, power management integrated circuits, voltage buffer. I.
Automated design of operational transconductance amplifiers using reversed geometric programming
 In Proceedings of the 41th IEEE/ACM Design Automation Conference
, 2004
"... We present a method for designing operational amplifiers using reversed geometric programming, which is an extension of geometric programming that allows both convex and nonconvex constraints. Adding a limited set of nonconvex constraints can improve the accuracy of convex equationbased optimizati ..."
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We present a method for designing operational amplifiers using reversed geometric programming, which is an extension of geometric programming that allows both convex and nonconvex constraints. Adding a limited set of nonconvex constraints can improve the accuracy of convex equationbased optimization, without compromising global optimality. These constraints allow increased accuracy for critical modeling equations, such as the relationship between gm and IDS. To demonstrate the design methodology, a foldedcascode amplifier is designed in a 0.18 µm technology for varying speed requirements and is compared with simulations and designs obtained from geometric programming. Categories and Subject Descriptors:
An Improved Model for the Slewing Behavior of Opamps
"... A new timedomain model for the slewing behavior of two stage opamps is presented. This model includes the effects of the load capacitance, compensation capacitance, device sizes and the nonlinear behavior of the transistors during the slewing period. This model improves on the commonly used constan ..."
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A new timedomain model for the slewing behavior of two stage opamps is presented. This model includes the effects of the load capacitance, compensation capacitance, device sizes and the nonlinear behavior of the transistors during the slewing period. This model improves on the commonly used constant current models and allows for more predictable designs. The model shows good agreement with simulations. Circuit design results using the traditional and new improved models are presented. 1 Introduction The settling time of an opamp is a very important parameter, particularly for switchedcapacitor and data converter circuits. The total settling time can be broken up into two distinct regions; a slewing period (TSL ) and a settling period (TST ) [1, 2]. During the slewing period the opamp operates in a rate limited fashion and the output voltage changes from its original value to a voltage close to its final value. And during the settling period the output voltage settles to its final v...
Design of RF/IF analog to digital converters for software radio communication receivers
, 2006
"... Software radio architecture can support multiple standards by performing analogtodigital (A/D) conversion of the radio frequency (RF) signals and running reconfigurable software programs on the backend digital signal processor (DSP). A slight variation of this architecture is the software defined ..."
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Software radio architecture can support multiple standards by performing analogtodigital (A/D) conversion of the radio frequency (RF) signals and running reconfigurable software programs on the backend digital signal processor (DSP). A slight variation of this architecture is the software defined radio architecture in which the A/D conversion is performed on intermediate frequency (IF) signals after a single down conversion. The first part of this research deals with the design and implementation of a fourth order continuous time bandpass sigmadelta (CT BP Σ∆) ADC based on LC filters for direct RF digitization at 950 MHz with a clock frequency of 3.8 GHz. A new ADC architecture is proposed which uses only nonreturn to zero feedback digital to analog converter pulses to mitigate problems associated with clock jitter. The architecture also has full control over tuning of the coefficients of the noise transfer function for obtaining iii the best signal to noise ratio (SNR) performance. The operation of the architecture is examined in detail and extra design parameters are introduced to ensure robust operation of the ADC. Measurement results of the ADC, implemented in IBM 0.25 µm SiGe
Advanced Analog Electronics Term Report Prepared by: Class Instructor
, 2001
"... Currently, there is an evergrowing demand for lowpower mixed signal integrated circuits for such applications as mobile or wired communications and other portable systems. In these applications, the supply voltage is being scaled down to reduce overall power consumption. As for the fabrication pro ..."
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Currently, there is an evergrowing demand for lowpower mixed signal integrated circuits for such applications as mobile or wired communications and other portable systems. In these applications, the supply voltage is being scaled down to reduce overall power consumption. As for the fabrication process, digital CMOS is always the preferred technology due to its efficient economic costs. As a result, contemporary analog circuits must not only operate with low supply voltages, but should also be realizable in typical digital CMOS processes. However, this concession leads to significant performance degradation of the analog circuits. Since op amps are the most critical building blocks in all analog systems, the objective of this report is to study the theory and design of low voltage op amps for digital CMOS processes. Two categories of low voltage op amps have been identified as being suitable for low voltage applications [1]. The first category operates with 23V power supplies. The distinct features of this class of op amps are that they utilize NP complementary, input pairs and the gain stages use active gain enhancement to boost the gain of the overall
A GainBoosted 90dB Dynamic Range Fast Settling OTA with 7.8mW Power Consumption
"... Abstract A fully differential highdynamic range operational transconductance amplifier (OTA) to be used in switchedcapacitor filters and/or oversampled A/D converters is presented. The architecture chosen for this design is folded cascode with fully differential gain boosting. It is demonstrated ..."
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Abstract A fully differential highdynamic range operational transconductance amplifier (OTA) to be used in switchedcapacitor filters and/or oversampled A/D converters is presented. The architecture chosen for this design is folded cascode with fully differential gain boosting. It is demonstrated through the design analysis and HSPICE simulation that such a structure realizes the best tradeoff between power consumption, speed, and dynamic range performances for this design. The OTA achieves a constant large signal DC gain (A DC) of> 84 dB over process and temperature variations. It is designed in a 0.35μm CMOS process and draws a DC power of 7.8 mW from a 3V supply. The achieved rms output noise voltage ( ) is 50.1 μV for the worst case scenario. With a peaktopeak output voltage swing (V o,pp) of 4.5 V, the achieved output dynamic range (DR) is 90 dB. The OTA also demonstrates excellent settling behavior with a singlepole rolloff frequency response and no overshoot or ringing is observed at the output when the required maximum 4V transient is applied at the input. The settling time to < 0.05 % accuracy for the worst case is ~ 19.5 ns. 1. INTRODUCTION TO GAINBOOSTING TECHNIQUE As CMOS design scales into lowpower lowvoltage regime, designing analog functional blocks under limited supply voltage becomes more and more difficult. One typical example is the basic gain stage. Cascoding is the mostly used technique to achieve high gain compared to 2stage designs because of its superior frequency
Especially
, 2005
"... Settling time is very important for data acquisition systems because it is the primary factor that defines the data rate for a given error level. Therefore settling time measurement is a crucial test. The goal of the project was to design, test and compare different measurement techniques. Three met ..."
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Settling time is very important for data acquisition systems because it is the primary factor that defines the data rate for a given error level. Therefore settling time measurement is a crucial test. The goal of the project was to design, test and compare different measurement techniques. Three methods were tested to the accuracies of 0.1% and 0.01%. Also simulations were conducted to explain the parameters that affect the settling behavior. Additionally bench measurements were correlated to simulation results. This report is intended as a guide for settling time measurements. ii Acknowledgements I would like to recognize key contributors to the completion of this thesis. I would like to thank, Professor John A. McNeill For his continuous assistance, guidance, and flexibility on this project, also For providing WPI Students with a well equipped Laboratory
jpvQeecs.berkeley.edu
"... We present a method for designing operational amplifiers using reversed geometric programming, which is an extension of geometric programming that allows both convex and nonconvex constraints. Adding a limited set of nonconvex constraints can improve the accuracy of convex equationbased optimizati ..."
Abstract
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We present a method for designing operational amplifiers using reversed geometric programming, which is an extension of geometric programming that allows both convex and nonconvex constraints. Adding a limited set of nonconvex constraints can improve the accuracy of convex equationbased optimization, without compromising global optimality. These constraints allow increased accuracy for critical modeling equations, such as the relationship between gm and Ips. To demonstrate the design methodology, a foldedcascode amplifier is designed in a 0.18'pm technology for varying speed requirements and is compared with simnlations and designs obtained from geometric programming. Categories and Subject Descriptors: