. This work presents the Brisk Machine, a machine model for the implementation of functional languages. It is especially designed to be flexible and dynamic, so that it can support a uniform and efficient implementation of multiple paradigms such as computational mobility, dynamic loading and linking, and logic programming. The Brisk Machine is based on the STG Machine, though its model is simplified and adapted so that the various paradigms it supports can be accommodated easily without interference between them. 1 Introduction Many different machine models have been proposed as intermediate forms in the compilation of functional languages, to act as the target of the front end of compilers and as a starting point for code generation. The resulting models tend to be complicated though, partly due to the effort to optimise them in a particular setting. The Brisk 1 Machine has been designed as a target for Haskell compilation which is flexible enough to support a number of different ...

Abstract. For the memory intensive task of graph reduction, modern PCs are limited not by processor speed, but by the rate that data can travel between processor and memory. This limitation is known as the von Neumann bottleneck. We explore the effect of widening this bottleneck using a special-purpose graph reduction machine with wide, parallel memories. Our prototype machine – the Reduceron – is implemented using an FPGA, and is based on a simple template-instantiation evaluator. Running at only 91.5MHz on an FPGA, the Reduceron is faster than mature bytecode implementations of Haskell running on a 2.8GHz PC. 1

The performance of program-derived combinator graph reduction is known to be superior to that of graph reduction based on a fixed set of standard combinator. The major advantage of program-derived combinator reduction is that it uses less transient store than standard combinator reduction. We show on what activities a combinator reduction algorithm spends its execution time. Based on this analysis we show that it depends to a large extent on the application how much faster a program will run if programderived combinator are used instead of standard combinator. The analysis is based on experimental evidence obtained from a small bench-mark of medium-size functional programs. Performance gains of up to 11 × are reported for target architectures on which each memory reference consumes one unit of time. The results are valid for implementations of combinator graph reduction that use binary graphs. KEY WORDS Turner’s combinator G-machine Performance modelling Graph reduction Instruction level timing Small functional bench-mark

The Hat system provides a method for tracing a lazy functional program. However Hat works by transforming the source program into a much larger self-tracing variant that runs between 15 and 100 times slower and uses several times as much memory. We show how equivalent traces can be generated much more efficiently by modifying the underlying abstract machine. Our approach shows that it is only necessary to add a few extra machine instructions and change the interpretation of a few others in order to generate Hat traces efficiently.

Set-based languages have emerged as a powerful means for expressing not only programs but also requirements, test cases and so on. However, a uniform compilation schema for sets has not yet been completely developed. The present paper tries to overcome this lack using a set-based logic language, SL (set language), as target. The approach is based on an imperative abstract machine, the SAM (set abstract machine). The translation from SL to SAL (SAM assembly language) is described and all the possible optimizations, both at source code level and at assembly code level, are detailed. The potentials for identifying parallel flows of computations are analysed. Several examples of compilations are presented and discussed.

A functional language compiler can be used as a powerful tool in the scheduling of programs for hardware capable of fine grained instruction level parallelism. There have been many attempts to effectively utilise functional languages as a means of easily programming parallel hardware. These attempts have generally concentrated on parallelising the underlying reduction strategies to achieve this goal. This paper explores an alternative use of a functional language compiler; as a tool for producing annotated code which can be effectively scheduled for the class of transport triggered architectures. These architectures are capable of much fine grained instruction level parallelism, and it is the task of the compiler to schedule code to utilise this power, in a manner similar to that of a compiler for a VLIW architecture. We believe that a functional language compiler has more freedom in the generation of code than imperative language compilers, due to the level of abstraction provided by ...

Machine [Car83], the G-machine [Joh84, BPJR88], Clean [BvEvLP87, KSvEP91], and DACTL [Ken88, GKS89]. All of these can be perceived as notations for algorithms that describe how graphs may be used to model the evaluation of the implemented language. Such notations have the advantage that they are directly executable. However, they are often not very readable since all the details of the implementation have to be present in the specification. On the other hand, the idea has also been used in attempts to build models of functional languages and to prove properties of such models directly. Again starting from [Wad71] such attempts are naturally focused on models of the -calculus---a 2 We will use the traditional word "redex" (reducible expression) rather than some abbreviation of "reducible subgraph" even though we will always refer to the latter. GRAPH-BASED OPERATIONAL SEMANTICS OF A LAZY FUNCTIONAL LANGUAGE 239 rather large are of research, so we will just mention [Sta78] and [Lam90...

To tag or not to tag: that is the question: Whether 'tis faster in the cache to suffer The delays of tagless nodes, Or break the pipe no more And make a branch that hits the cache. To load, to jump; To jump: perchance to stall; Ay, there's the run. 1 Introduction The paper on the HDG parallel machine [KLB91] contains an intruiging paragraph. Comparing Peyton Jones' and Salkild's Spineless Tagless G-Machine model [PeSa89] with the <n,G>- Machine [AuJo89], Kingdon, Lester and Burn observe that In theory Augustsson and Johnsson are right. ... In practice, on traditional hardware Peyton Jones and Salkild are correct. Many new architectures have been proposed since the original Spineless Tagless G-Machine was first designed. In particular, RISC chips have become commonplace, and features which used to be confined to supercomputers or large mainframes, such as pipelined execution or multiple independent instruction units, are now commonly available on single-chip microprocessors. This paper ...

We describe a technique for incorporating Baker's incremental garbage collection algorithm into the Spineless Tagless G-machine on stock hardware. This algorithm eliminates the stop/go execution associated with bulk copying collection algorithms, allowing the system to place an upper bound on the time taken to perform a store operation. The implementation is based on the manipulation of code-pointers and is considerably more efficient than previous software implementations of Baker's algorithm. 1 Introduction A significant drawback of automatic garbage collection is its detrimental effect on the responsiveness of a program. While the system is collecting garbage it is unavailable to user programs for useful work, and this can cause a program to appear `dead' for extended periods of time. This problem is caused largely by the fact that garbage collection algorithms typically collect all of the system's free store in one go, an operation that takes time at least proportional to the numb...

Abstract: Experience shows that users of the Hat viewing tools find it hard to keep orientation and navigate to a point of interest in the trace. Hence this paper describes a new viewing tool where navigation through the trace is based on the program source. The tool combines ideas from algorithmic debugging, traditional stepping debuggers and dynamic program slicing. 1