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39
GRASP  A New Search Algorithm for Satisfiability
, 1996
"... This paper introduces GRASP (Generic seaRch Algorithm for the Satisjiability Problem), an integrated algorithmic framework for SAT that un.$es several previously proposed searchpruning techniques and facilitates ident$cation of additional ones. GRASP is premised on the inevitability of confzicts dur ..."
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Cited by 358 (28 self)
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This paper introduces GRASP (Generic seaRch Algorithm for the Satisjiability Problem), an integrated algorithmic framework for SAT that un.$es several previously proposed searchpruning techniques and facilitates ident$cation of additional ones. GRASP is premised on the inevitability of confzicts during search and its most distinguishing feature is the augmentation of basic backtracking search with a powerfil confzict analysis procedure. Analyzing confzicts to determine their cawes enables GRASP to backtrack nonchronologically to earlier levels in the search tree, potentially pruning large portions of the search space. In addition, by “recording ” the causes of conflicts, GRASP can recognize andpreempt the occurrence of similar conficts later on in the search. Finally, straightjwward bookkeeping of the causality chains leading up to conflicts allows GRASP to identifi assignments that are necessary for a solution to be found. fiperimental results obtained from a large number of benchmarks, including many from the $eld of test pattern generation, indicate that application of the proposed confzict analysis techniques to SATalgorithm can be extremely effectivefor a large number of representative classes of SAT instances. 1
Robust search algorithms for test pattern generation
 in Proceedings of the FaultTolerant Computing Symposium
, 1997
"... In recent years several highly effective algorithms have been proposed for Automatic Test Pattem Generation (ATPG). Nevertheless, most of these algorithms too ojien rely on different types of heuristics to achieve good empirical performance. Moreovel; there has not been signgcant research work on d ..."
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Cited by 45 (13 self)
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In recent years several highly effective algorithms have been proposed for Automatic Test Pattem Generation (ATPG). Nevertheless, most of these algorithms too ojien rely on different types of heuristics to achieve good empirical performance. Moreovel; there has not been signgcant research work on developing algorithms that are robust, in the sense that they can handle most faults with little heuristic guidance. In this paper we describe an algorithm for ATPG that is robust and still very efficient. In contrast with existing algorithms for ATPG, the proposed algorithm reduces heuristic knowledge to a minimum and relies on an optimized search algorithm for effectively pruning the search space. Even though the experimental results are obtained using an ATPG tool built on top of a Propositional Satisfability (SAT) algorithm, the same concepts can be integrated on applicationspeciJc algorithms. 1
New Techniques for Deterministic Test Pattern Generation
 Journal of Electronic Testing: Theory and Applications
, 1999
"... This paper presents new techniques for speeding up deterministic test pattern generation for VLSI circuits. These techniques improve the PODEM algorithm by reducing number of backtracks with a low computational cost. This is achieved by finding more necessary signal line assignments, by detecting co ..."
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Cited by 40 (3 self)
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This paper presents new techniques for speeding up deterministic test pattern generation for VLSI circuits. These techniques improve the PODEM algorithm by reducing number of backtracks with a low computational cost. This is achieved by finding more necessary signal line assignments, by detecting conflicts earlier, and by avoiding unnecessary work during test generation. We have incorporated these techniques into an advanced ATPG system for combinational circuits, called ATOM. The performance results for the ISCAS85 and full scan version of the ISCAS89 benchmark circuits demonstrated the effectiveness of these techniques on the test generation performance. ATOM detected all the testable faults and proved all the redundant faults to be redundant with a small number of backtracks in a short amount of time. 1 Introduction As the complexity of VLSI circuits and their quality requirements are increasing, the problem of test generation is becoming more important. Since the scanbased desig...
FIRE: A FaultIndependent Combinational Redundancy Identification Algorithm
 IEEE Transactions on VLSI Systems
, 1996
"... FIRE is a novel FaultIndependent algorithm for combinational REdundancy identification. The algorithm is based on a simple concept that a fault which requires a conflict as a necessary condition for its detection is undetectable and hence redundant. FIRE does not use the backtrackingbased exhausti ..."
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Cited by 25 (0 self)
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FIRE is a novel FaultIndependent algorithm for combinational REdundancy identification. The algorithm is based on a simple concept that a fault which requires a conflict as a necessary condition for its detection is undetectable and hence redundant. FIRE does not use the backtrackingbased exhaustive search performed by faultoriented automatic test generation algorithms, and identifies redundant faults without any search. Our results on benchmark and real circuits indicate that we find a large number of redundancies, much faster than a testgenerationbased approach for redundancy identification. However, FIRE is not guaranteed to identify all redundancies in a circuit. ______________ Index terms: Redundancy identification, automatic test generation, logic synthesis 1. Introduction An automatic test generation (ATG) algorithm spends a large portion of its time dealing with undetectable faults. A fault is undetectable if there exists no test to detect it. A fault is identified as ...
An exact solution to the minimum size test pattern problem
 in Proc. International Conference on Computer Design (ICCD
, 1998
"... This article addresses the problem of test pattern generation for single stuckat faults in combinational circuits, under the additional constraint that the number of specified primary input assignments is minimized. This problem has different applications in testing, including the identification of ..."
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Cited by 15 (0 self)
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This article addresses the problem of test pattern generation for single stuckat faults in combinational circuits, under the additional constraint that the number of specified primary input assignments is minimized. This problem has different applications in testing, including the identification of “don’t care ” conditions to be used in the synthesis of BuiltIn SelfTest (BIST) logic. The proposed solution is based on an integer linear programming (ILP) formulation which builds on an existing Propositional Satisfiability (SAT) model for test pattern generation. The resulting ILP formulation is linear on the size of the original SAT model for test generation, which is linear on the size of the circuit. Nevertheless, the resulting ILP instances represent complex optimization problems, that require dedicated ILP algorithms. Preliminary results on benchmark circuits validate the practical applicability of the test pattern minimization model and associated ILP algorithm.
Layout driven logic synthesis for FPGAs
"... In this paper, we propose a layout driven synthesis approach for Field Programmable Gate Arrays (FPGAs). The approach attempts ..."
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Cited by 15 (1 self)
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In this paper, we propose a layout driven synthesis approach for Field Programmable Gate Arrays (FPGAs). The approach attempts
Redundancy Identification Using Transitive Closure
 in Proc. of the 5th Asian Test Symp
, 1996
"... We analyze all signals of a combinational circuit simultaneously for redundancy. The state of a signal is represented by two binary variables. The first variable is the logic value of the signal. The second variable is the observability status of the signal with respect to all primary outputs. Boole ..."
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Cited by 11 (5 self)
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We analyze all signals of a combinational circuit simultaneously for redundancy. The state of a signal is represented by two binary variables. The first variable is the logic value of the signal. The second variable is the observability status of the signal with respect to all primary outputs. Boolean equations specify local relationships of these variables in a manner similar to the neural network or Boolean satisfiability method. All pairwise terms appearing in these Boolean equations are used to construct an implication graph, for which the transitive closure graph is obtained. Any signal assignments or relations found from the transitive closure are substituted into higherorder terms of the Boolean equations, some of which reduce to pairwise terms. Such cases are iteratively included in the transitive closure until no more reductions are possible. In the final transitive closure, all signals are examined for the following conditions of redundancy: (1) If a signal and its complement imply each other (contradiction) then both stuckat faults on that signal are redundant; (2) If one value implies the other value (fixation) then one of the stuckat faults on that signal is redundant; (3) If the true observability status of a signal implies its own false observability status, then both stuckat faults of that signal are redundant; (4) If a certain value of a signal implies the false observability status, then the corresponding stuckat fault is redundant. Despite the apparent similarities with the transitive closure based ATPG, the present method is quite different. Here transitive closure is computed just once, and not recomputed or updated separately for each fault as required in ATPG. We give ISCAS '85 benchmark results. For c6288, we could identify 31 out of 33 redu...
Efficient Search Techniques for the Inference of Minimum Size Finite Automata
 In Proceedings of the 1998 South American Symposium on String Processing and Information Retrieval, Santa Cruz de La Sierra
, 1998
"... We propose a new algorithm for the inference of the minimum size deterministic automaton consistent with a prespecified set of input/output strings. Our approach improves a well known search algorithm proposed by Bierman, by incorporating a set of techniques known as dependency directed backtracking ..."
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Cited by 11 (2 self)
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We propose a new algorithm for the inference of the minimum size deterministic automaton consistent with a prespecified set of input/output strings. Our approach improves a well known search algorithm proposed by Bierman, by incorporating a set of techniques known as dependency directed backtracking. These techniques have already been used in other applications, but we are the first to apply them to this problem. The results show that the application of these techniques yields an algorithm that is, for the problems studied, orders of magnitude faster than existing approaches.
A FaultIndependent Transitive Closure Algorithm for Redundancy Identification
 IN PROC. OF THE 16 TH INTERNATIONAL CONF. VLSI DESIGN
, 2003
"... We present a faultindependent redundancy identification algorithm. The controllabilities and observabilities are defined as Boolean variables and represented on an implication graph. A major enhancement over previously published results is that we include all direct and partial implications, as we ..."
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Cited by 8 (5 self)
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We present a faultindependent redundancy identification algorithm. The controllabilities and observabilities are defined as Boolean variables and represented on an implication graph. A major enhancement over previously published results is that we include all direct and partial implications, as well as node fixation. The transitive closure, whose computation now requires a new algorithm, provides many redundant faults in a singlepass analysis. Because of these improvements, we obtain better performance than all previous faultindependent methods at execution speeds that are much faster than any exhaustive ATPG. For example, in the s9234 circuit more than half of the redundant faults are found in just 14 seconds on a Sparc 5. All 34 redundant faults of c6288 are found in one pass. Besides, our single pass procedure can classify faults according to the causes of their redundancy. The weakness of our method, as we illustrate by examples, lies in the lack of a formulation for the observabilities of fanout stems.
An Exact Solution to the MinimumSize Test Pattern Problem
 In Proceedings of the IEEE International Conference on Computer Design
, 1998
"... This paper addresses the problem of test pattern generation for single stuckat faults in combinational circuits, under the additional constraint that the number of specified primary input assignments is minimized. This problem has different applications in testing, including the identification of d ..."
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Cited by 7 (4 self)
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This paper addresses the problem of test pattern generation for single stuckat faults in combinational circuits, under the additional constraint that the number of specified primary input assignments is minimized. This problem has different applications in testing, including the identification of don't care conditions to be used in the synthesis of BuiltIn SelfTest (BIST) logic. The proposed solution is based on an integer linear programming (ILP) formulation which builds on an existing Propositional Satisfiability (SAT) model for test pattern generation. The resulting ILP formulation is linear on the size of the original SAT model for test generation, which is linear on the size of the circuit. Nevertheless, the resulting ILP instances represent complex optimization problems, that require dedicated ILP algorithms. Preliminary results on benchmark circuits validate the practical applicability of the test pattern minimization model and associated ILP algorithm. 1 Introduction Auto...