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13
Asymptotic Probability Extraction for NonNormal Distributions of Circuit Performance
 IEEE ICCAD
, 2004
"... While process variations are becoming more significant with each new IC technology generation, they are often modeled via linear regression models so that the resulting performance variations can be captured via Normal distributions. Nonlinear (e.g. quadratic) response surface models can be utilized ..."
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Cited by 46 (7 self)
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While process variations are becoming more significant with each new IC technology generation, they are often modeled via linear regression models so that the resulting performance variations can be captured via Normal distributions. Nonlinear (e.g. quadratic) response surface models can be utilized to capture larger scale process variations; however, such models result in nonNormal distributions for circuit performance which are difficult to capture since the distribution model is unknown. In this paper we propose an asymptotic probability extraction method, APEX, for estimating the unknown random distribution when using nonlinear response surface modeling. APEX first uses a novel binomial moment evaluation to efficiently compute the high order moments of the unknown distribution, and then applies moment matching to approximate the characteristic function of the random circuit performance by an efficient rational function. A simple statistical timing example and an analog circuit example demonstrate that APEX can provide better accuracy than Monte Carlo simulation with 10 4 samples and achieve orders of magnitude more efficiency. We also show the error incurred by the popular Normal modeling assumption using standard IC technologies. 1.
Robust analog/RF circuit design with projectionbased posynomial modeling
 IEEE/ACM ICCAD
, 2004
"... In this paper we propose a RObust Analog Design tool (ROAD) for posttuning analog/RF circuits. Starting from an initial design derived from hand analysis or analog circuit synthesis based on simplified models, ROAD extracts accurate posynomial performance models via transistorlevel simulation and ..."
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Cited by 24 (9 self)
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In this paper we propose a RObust Analog Design tool (ROAD) for posttuning analog/RF circuits. Starting from an initial design derived from hand analysis or analog circuit synthesis based on simplified models, ROAD extracts accurate posynomial performance models via transistorlevel simulation and optimizes the circuit by geometric programming. Importantly, ROAD sets up all design constraints to include largescale process variations to facilitate the tradeoff between yield and performance. A novel convex formulation of the robust design problem is utilized to improve the optimization efficiency and to produce a solution that is superior to other local tuning methods. In addition, a novel projectionbased approach for posynomial fitting is used to facilitate scaling to large problem sizes. A new implicit power iteration algorithm is proposed to find the optimal projection space and extract the posynomial coefficients with robust convergence. The efficacy of ROAD is demonstrated on several circuit examples. 1.
Projectionbased performance modeling for inter/intradie variations
 in Proc. IEEE/ACM Int. Conf. Comput.Aided Des., 2005
, 2005
"... Largescale process fluctuations in nanoscale IC technologies suggest applying highorder (e.g., quadratic) response surface models to capture the circuit performance variations. Fitting such models requires significantly more simulation samples and solving much larger linear equations. In this pap ..."
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Cited by 19 (10 self)
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Largescale process fluctuations in nanoscale IC technologies suggest applying highorder (e.g., quadratic) response surface models to capture the circuit performance variations. Fitting such models requires significantly more simulation samples and solving much larger linear equations. In this paper, we propose a novel projectionbased extraction approach, PROBE, to efficiently create quadratic response surface models and capture both interdie and intradie variations with affordable computation cost. PROBE applies a novel projection scheme to reduce the response surface modeling cost (i.e., both the required number of samples and the linear equation size) and make the modeling problem tractable even for large problem sizes. In addition, a new implicit power iteration algorithm is developed to find the optimal projection space and solve for the unknown model coefficients. Several circuit examples from both digital and analog circuit modeling applications demonstrate that PROBE can generate accurate response surface models while achieving up to 12x speedup compared with the traditional methods. 1.
Asymptotic probability extraction for nonnormal performance distributions
 IEEE TRANS. CAD
, 2007
"... While process variations are becoming more significant with each new IC technology generation, they are often modeled via linear regression models so that the resulting performance variations can be captured via normal distributions. Nonlinear response surface models (e.g., quadratic polynomials) c ..."
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Cited by 18 (9 self)
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While process variations are becoming more significant with each new IC technology generation, they are often modeled via linear regression models so that the resulting performance variations can be captured via normal distributions. Nonlinear response surface models (e.g., quadratic polynomials) can be utilized to capture larger scale process variations; however, such models result in nonnormal distributions for circuit performance. These performance distributions are difficult to capture efficiently since the distribution model is unknown. In this paper, an asymptoticprobabilityextraction (APEX) method for estimating the unknown random distribution when using a nonlinear response surface modeling is proposed. The APEX begins by efficiently computing the highorder moments of the unknown distribution and then applies moment matching to approximate the characteristic function of the random distribution by an efficient rational function. It is proven that such a momentmatching approach is asymptotically convergent when applied to quadratic response surface models. In addition, a number of novel algorithms and methods, including binomial moment evaluation, PDF/CDF shifting, nonlinear companding and reverse evaluation, are proposed to improve the computation efficiency and/or approximation accuracy. Several circuit examples from both digital and analog applications demonstrate that APEX can provide better accuracy than a Monte Carlo simulation with 104 samples and achieve up to 10 × more efficiency. The error, incurred by the popular normal modeling assumption for several circuit examples designed in standard IC technologies, is also shown.
Beyond loworder statistical response surfaces: latent variable regression for efficient, highly nonlinear fitting
 IEEE DAC
, 2007
"... The number and magnitude of process variation sources are increasing as we scale further into the nano regime. Today’s most successful response surface methods limit us to loworder forms linear, quadratic to make the fitting tractable. Unfortunately, not all variational scenarios are well model ..."
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Cited by 14 (2 self)
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The number and magnitude of process variation sources are increasing as we scale further into the nano regime. Today’s most successful response surface methods limit us to loworder forms linear, quadratic to make the fitting tractable. Unfortunately, not all variational scenarios are well modeled with loworder surfaces. We show how to exploit latent variable regression ideas to support efficient extraction of arbitrarily nonlinear statistical response surfaces. An implementation of these ideas called SiLVR, applied to a range of analog and digital circuits, in technologies from 90 to 45nm, shows significant improvements in prediction, with errors reduced by up to 21X, with very reasonable runtime costs.
Statistical Performance Modeling and Optimization
"... As IC technologies scale to finer feature sizes, it becomes increasingly difficult to control the relative process variations. The increasing fluctuations in manufacturing processes have introduced unavoidable and significant uncertainty in circuit performance; hence ensuring manufacturability has b ..."
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Cited by 9 (5 self)
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As IC technologies scale to finer feature sizes, it becomes increasingly difficult to control the relative process variations. The increasing fluctuations in manufacturing processes have introduced unavoidable and significant uncertainty in circuit performance; hence ensuring manufacturability has been identified as one of the top priorities of today’s IC design problems. In this paper, we review various statistical methodologies that have been recently developed to model, analyze, and optimize performance variations at both transistor level and system level. The following topics will be discussed in detail: sources of process variations, variation characterization and modeling, Monte Carlo analysis, response surface modeling, statistical timing and leakage analysis, probability distribution extraction, parametric yield estimation and robust IC optimization. These techniques provide the necessary CAD infrastructure that facilitates the bold move from deterministic, cornerbased IC design toward statistical and probabilistic design. 1
Efficient Parametric Yield Estimation of Analog/Mixed Signal Circuits via Bayesian Model Fusion
"... Parametric yield estimation is one of the most criticalyetchallenging tasks for designing and verifying nanoscale analog and mixedsignal circuits. In this paper, we propose a novel Bayesian model fusion (BMF) technique for efficient parametric yield estimation. Our key idea is to borrow the simula ..."
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Cited by 5 (4 self)
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Parametric yield estimation is one of the most criticalyetchallenging tasks for designing and verifying nanoscale analog and mixedsignal circuits. In this paper, we propose a novel Bayesian model fusion (BMF) technique for efficient parametric yield estimation. Our key idea is to borrow the simulation data from an early stage (e.g., schematiclevel simulation) to efficiently estimate the performance distributions at a late stage (e.g., postlayout simulation). BMF statistically models the correlation between earlystage and latestage performance distributions by Bayesian inference. In addition, a convex optimization is formulated to solve the unknown latestage performance distributions both accurately and robustly. Several circuit examples designed in a commercial 32 nm CMOS process demonstrate that the proposed BMF technique achieves up to 3.75 × runtime speedup over the traditional kernel estimation method. 1.
Quadratic Statistical MAX Approximation for Parametric Yield Estimation of Analog/RF Integrated Circuits
"... Abstract—In this paper, we propose an efficient numerical algorithm for estimating the parametric yield of analog/RF circuits, considering largescale process variations. Unlike many traditional approaches that assume normal performance distributions, the proposed approach is particularly developed ..."
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Cited by 4 (2 self)
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Abstract—In this paper, we propose an efficient numerical algorithm for estimating the parametric yield of analog/RF circuits, considering largescale process variations. Unlike many traditional approaches that assume normal performance distributions, the proposed approach is particularly developed to handle multiple correlated nonnormal performance distributions, thereby providing better accuracy than the traditional techniques. Starting from a set of quadratic performance models, the proposed parametric yield estimation conceptually maps multiple correlated performance constraints to a single auxiliary constraint by using a MAX operator. As such, the parametric yield is uniquely determined by the probability distribution of the auxiliary constraint and, therefore, can easily be computed. In addition, two novel numerical algorithms are derived from moment matching and statistical Taylor expansion, respectively, to facilitate efficient quadratic statistical MAX approximation. We prove that these two algorithms are mathematically equivalent if the performance distributions are normal. Our numerical examples demonstrate that the proposed algorithm provides an error reduction of 6.5 times compared to a normaldistributionbased method while achieving a runtime speedup of 10–20 times over the Monte Carlo analysis with 103 samples. Index Terms—Analog/RF circuits, MAXoperator, parametric yield.
Bayesian Model Fusion: LargeScale Performance Modeling of Analog and MixedSignal Circuits by Reusing EarlyStage Data
"... Efficient highdimensional performance modeling of today’s complex analog and mixedsignal (AMS) circuits with largescale process variations is an important yet challenging task. In this paper, we propose a novel performance modeling algorithm that is referred to as Bayesian Model Fusion (BMF). Our ..."
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Cited by 2 (1 self)
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Efficient highdimensional performance modeling of today’s complex analog and mixedsignal (AMS) circuits with largescale process variations is an important yet challenging task. In this paper, we propose a novel performance modeling algorithm that is referred to as Bayesian Model Fusion (BMF). Our key idea is to borrow the simulation data generated from an early stage (e.g., schematic level) to facilitate efficient highdimensional performance modeling at a late stage (e.g., post layout) with low computational cost. Such a goal is achieved by statistically modeling the performance correlation between early and late stages through Bayesian inference. Several circuit examples designed in a commercial 32nm CMOS process demonstrate that BMF achieves up to 9 × runtime speedup over the traditional modeling technique without surrendering any accuracy. 1.
Sparse Statistical Model Inference for Analog Circuits under Process Variations
"... Abstract — In this paper, we address the problem of performance modeling for transistorlevel circuits under process variations. A sparse regression technique is introduced to characterize the relationship between the process parameters and the output responses. This approach relies on repeated sim ..."
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Cited by 1 (1 self)
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Abstract — In this paper, we address the problem of performance modeling for transistorlevel circuits under process variations. A sparse regression technique is introduced to characterize the relationship between the process parameters and the output responses. This approach relies on repeated simulations to find polynomial approximations of response surfaces. It employs a heuristic to construct sparse polynomial expansions and a stepwise regression algorithm based on LASSO to find low degree polynomial approximations. The proposed technique is able to handle many tens of process parameters with a small number of simulations when compared to an earlier approach using ordinary least squares. We present our approach in the context of statistical model inference (SMI), a recently proposed statistical verification framework for transistorlevel circuits. Our experimental evaluation compares percentage yields predicted by our approach with MonteCarlo simulations and SMI using ordinary least squares on benchmarks with up to 30 process parameters. The sparseSMI approach is shown to require significantly fewer simulations, achieving orders of magnitude improvement in the run times with small differences in the resulting yield estimates. I.