Abstract—A low-energy successive approximation analog-todigital converter (ADC) targeted for use in distributed sensor networks is presented. The individual nodes combine sensing, computation, communications, and power into a tiny volume. Energy is extremely limited, forcing the nodes to operate with very low duty cycles. This paper describes the design and implementation of an ADC to meet the unique requirements of sensor networks. The ADC reported here consumes 31 pJ/8-bit sample at 1-V supply and 100 kS/s, with a standby power consumption of 70 pW. This energy consumption is one of the lowest ever reported. Index Terms—Analog-to-digital converter (ADC), charge redistribution, CMOS, energy, low power, sensor networks, Smart Dust, successive approximation.

A successive approximation ADC targeted for use in distributed sensor networks is presented. The individual nodes in these sensor networks are very energy constrained. Typical use of the individual nodes will include long periods of idle time in a low power standby mode followed by a period of activity that may include sampling of the sensors, computation, and communication. The ADC reported here consumes only 3.1 µW, resulting in 31 pJ/8-bit sample at 1V supply with a maximum sampling rate slightly over 100 kS/s. The standby power consumption at 1 V supply is 41 pW. The µ-power consumption makes this one of the lowest power ADCs ever reported. 1.

The analog-to-digital converter (ADC) is an essential part of system-on-chip (SoC) products because it bridges the gap between the analog physical world and the digital logical world. In the digital domain, low power and low voltage requirements are be-coming more important issues as the channel length of MOSFET shrinks below 0.25 sub-micron values. Moreover, SoC trends force ADCs to be integrated on the chip with other digital circuits. These trends present new challenges in ADC circuit design. Thus, this thesis is to investigate high speed, low power, and low voltage CMOS flash ADCs for SoC applications. The proposed ADC utilizes the Threshold Inverter Quantization (TIQ) technique that uses two cascaded CMOS inverters as a comparator. The TIQ technique has been introduced in [53]. The TIQ technique proposed here has been developed for better implementation in SoC applications. Four issues are addressed to achieve high speed, low power consumption, and low voltage operation in the TIQ flash ADC. First, the high speed and low power TIQ flash ADC architecture is presented along with an optimal

The continued drive toward technology scaling in VLSI design has provided greater integration levels in silicon chips. Thanks to the reduction in minimum feature size and the corresponding decrease in power supply voltage, digital circuits have bene-fited from savings in area and power consumption. This approach presents a number of challenges in Complementary Metal-Oxide Semiconductor (CMOS) analog circuit design. As the gate oxide of transistors becomes thinner and power consumption increases, a lower supply voltage must be used, even though it results in performance degradation of analog circuits. This must be done in order to avoid silicon punch-through. In applications requiring low power consumption and moderate conversion speed, one of the most frequently used analog-to-digital converter (ADC) architec-tures is the successive approximation. As data converters are mixed-signal circuits, containing both analog and digital circuits, they suffer from the same problems just described. This thesis presents the design of a low-voltage successive approximation ADC based on a Switched Opamp comparator. The proposed comparator archi-

A CMOS flash analog-to-digital converter (ADC) designed for high speed and low voltage is presented. Using the Threshold Inverter Quantization (TIQ) comparator technique, a flash ADC can be applied to low supply voltage. A fat tree encoder that has signal delay of O(log2N) is used for performance. A 6-bit and an 8-bit flash ADC were designed with 0.07 µm CMOS technology and 0.7 V power supply voltage. The 6-bit ADC operates up to 4.76 giga samples per second (GSPS) with 11.35 mW power consumption. In case of the 8-bit ADC, it consumes 48.90 mW at its highest speed 3.57 GSPS.

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