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36
Spanning Trees and Spanners
, 1996
"... We survey results in geometric network design theory, including algorithms for constructing minimum spanning trees and lowdilation graphs. 1 Introduction This survey covers topics in geometric network design theory. The problem is easy to state: connect a collection of sites by a "good" network. ..."
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Cited by 139 (2 self)
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We survey results in geometric network design theory, including algorithms for constructing minimum spanning trees and lowdilation graphs. 1 Introduction This survey covers topics in geometric network design theory. The problem is easy to state: connect a collection of sites by a "good" network. For instance, one may wish to connect components of a VLSI circuit by networks of wires, in a way that uses little surface area on the chip, draws little power, and propagates signals quickly. Similar problems come up in other applications such as telecommunications, road network design, and medical imaging [1]. One network design problem, the Traveling Salesman problem, is sufficiently important to have whole books devoted to it [79]. Problems involving some form of geometric minimum or maximum spanning tree also arise in the solution of other geometric problems such as clustering [12], mesh generation [56], and robot motion planning [93]. One can vary the network design problem in many w...
Performance optimization of VLSI interconnect layout
 Integration, the VLSI Journal
, 1996
"... This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for highperformance VLSI circuit design under the deep submicron fabrication technologies. ..."
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Cited by 102 (32 self)
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This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for highperformance VLSI circuit design under the deep submicron fabrication technologies. First, we present a number of interconnect delay models and driver/gate delay models of various degrees of accuracy and efficiency which are most useful to guide the circuit design and interconnect optimization process. Then, we classify the existing work on optimization of VLSI interconnect into the following three categories and discuss the results in each category in detail: (i) topology optimization for highperformance interconnects, including the algorithms for total wire length minimization, critical path length minimization, and delay minimization; (ii) device and interconnect sizing, including techniques for efficient driver, gate, and transistor sizing, optimal wire sizing, and simultaneous topology construction, buffer insertion, buffer and wire sizing; (iii) highperfbrmance clock routing, including abstract clock net topology generation and embedding, planar clock routing, buffer and wire sizing for clock nets, nontree clock routing, and clock schedule optimization. For each method, we discuss its effectiveness, its advantages and limitations, as well as its computational efficiency. We group the related techniques according to either their optimization techniques or optimization objectives so that the reader can easily compare the quality and efficiency of different solutions.
Zero Skew Clock Routing With Minimum Wirelength
, 1992
"... In the design of high performance VLSI systems, minimization of clock skew is an increasingly important objective. Additionally, wirelength of clock routing trees should be minimized in order to reduce system power requirements and deformation of the clock pulse at the synchronizing elements of the ..."
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Cited by 73 (12 self)
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In the design of high performance VLSI systems, minimization of clock skew is an increasingly important objective. Additionally, wirelength of clock routing trees should be minimized in order to reduce system power requirements and deformation of the clock pulse at the synchronizing elements of the system. In this paper, we first present the DeferredMerge Embedding (DME) algorithm, which embeds any given connection topology to create a clock tree with zero skew while minimizing total wirelength. The algorithm always yields exact zero skew trees with respect to the appropriate delay model. Experimental results show an 8% to 15% wirelength reduction over previous constructions in [17] [18]. The DME algorithm may be applied to either the Elmore or linear delay model, and yields optimal total wirelength for linear delay. DME is a very fast algorithm, running in time linear in the number of synchronizing elements. We also present a unified BB+DME algorithm, which constructs a clock tree t...
Clock Distribution Networks in Synchronous Digital Integrated Circuits
 Proc. IEEE
, 2001
"... this paper, bears separate focus. The paper is organized as follows. In Section II, an overview of the operation of a synchronous system is provided. In Section III, fundamental definitions and the timing characteristics of clock skew are discussed. The timing relationships between a local data path ..."
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Cited by 56 (5 self)
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this paper, bears separate focus. The paper is organized as follows. In Section II, an overview of the operation of a synchronous system is provided. In Section III, fundamental definitions and the timing characteristics of clock skew are discussed. The timing relationships between a local data path and the clock skew of that path are described in Section IV. The interplay among the aforementioned three subsystems making up a synchronous digital system is described in Section V; particularly, how the timing characteristics of the memory and logic elements constrain the design and synthesis of clock distribution networks. Different forms of clock distribution networks, such as buffered trees and Htrees, are discussed. The automated layout and synthesis of clock distribution networks are described in Section VI. Techniques for making clock distribution networks less sensitive to process parameter variations are discussed in Section VII. Localized scheduling of the clock delays is useful in optimizing the performance of highspeed synchronous circuits. The process for determining the optimal timing characteristics of a clock distribution network is reviewed in Section VIII. The application of clock distribution networks to highspeed circuits has existed for many years. The design of the clock distribution network of certain important VLSIbased systems has been described in the literature, and some examples of these circuits are described in Section IX. In an effort to provide some insight into future and evolving areas of research relevant to highperformance clock distribution networks, some potentially important topics for future research are discussed in Section X. Finally, a summary of this paper with some concluding remarks is provided in Section XI
ZeroSkew Clock Routing Trees With Minimum Wirelength
 Proc. IEEE Intl. Conf. on ASIC
, 1992
"... In the design of high performance VLSI systems, minimization of clock skew is an increasingly important objective. Additionally, wirelength of clock routing trees should be minimized in order to reduce system power requirements and deformation of the clock pulse at the synchronizing elements of the ..."
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Cited by 49 (13 self)
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In the design of high performance VLSI systems, minimization of clock skew is an increasingly important objective. Additionally, wirelength of clock routing trees should be minimized in order to reduce system power requirements and deformation of the clock pulse at the synchronizing elements of the system. In this paper, we present the DeferredMerge Embedding (DME) algorithm, which in linear time embeds any given connection topology into the Manhattan plane to create a clock tree with zero skew while minimizing total wirelength. Extensive experimental results show that the algorithm yields exact zero skew trees with 9% to 16% wirelength reduction over previous constructions [5] [6]. The DME algorithm may be applied to either the Elmore or the linear delay model, and yields optimal total wirelength for linear delay. 1 Introduction In synchronous VLSI designs, circuit speed is increasingly limited by clock skew, which is the maximum difference in arrival times of the clocking signal ...
A Graphtheoretic Approach to ClockSkew Optimization
 In Proc. International Symp. on Circuits and Systems
, 1994
"... This paper addresses the problem of minimizing the clock period of a circuit by optimizing the clockskews. We incorporate uncertainty factors and present a formulation that ensures that the optimization will be safe. In (1), the problem of clock period optimization is formulated as a linear program. ..."
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Cited by 39 (3 self)
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This paper addresses the problem of minimizing the clock period of a circuit by optimizing the clockskews. We incorporate uncertainty factors and present a formulation that ensures that the optimization will be safe. In (1), the problem of clock period optimization is formulated as a linear program. We first propose an efficient graphbased solution that takes advantage of the structure of the problem. We also show that the results of (1) may result in exceedingly large skews, and propose a method to reduce these skews without sacrificing the optimality of the clock period. Experimental results on several ISCAS89 benchmark circuits are provided.
Utilizing the RetimingSkew Equivalence in a Practical Algorithm for Retiming Large Circuits
 IEEE Transactions on VLSI Systems
, 1996
"... this paper, and a great deal of e#ort has been invested into researchin this #eld. This paper considers the method of retiming #1#, which proceeds by relocating #ip#ops within a network to achieve faster clocking speeds. A novel approach to retiming that utilizes the solution of the clockskew opti ..."
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Cited by 27 (0 self)
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this paper, and a great deal of e#ort has been invested into researchin this #eld. This paper considers the method of retiming #1#, which proceeds by relocating #ip#ops within a network to achieve faster clocking speeds. A novel approach to retiming that utilizes the solution of the clockskew optimization problem #2# forms the backbone of this work
MatchingBased Methods for HighPerformance Clock Routing
 IEEE TRANS. ON CAD
, 1993
"... Minimizing clock skew is important in the design of high performance VLSI systems. We present a general clock routing scheme that achieves very small clock skews while still using a reasonable amount of wirelength. Our routing solution is based on the construction of a binary tree using geometric ma ..."
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Cited by 24 (7 self)
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Minimizing clock skew is important in the design of high performance VLSI systems. We present a general clock routing scheme that achieves very small clock skews while still using a reasonable amount of wirelength. Our routing solution is based on the construction of a binary tree using geometric matching. For cellbased designs, the total wirelength of our clock routing tree is on average within a constant factor of the wirelength in an optimal Steiner tree, and in the worst case is bounded by O(/x//  n) for n terminals arbitrarily distrib uted in the It x 12 grid. The bottomup construction readily extends to general cell layouts, where it also achieves essentially zero clock skew within reasonably bounded total wirelength. We have tested our algorithms on numerous random examples and also on layouts of industrial benchmark circuits. The results are promising: our clock routing yields nearzero average clock skew while using total wirelength competitive with previously known methods.
Automatic Synthesis of Gated Clocks for Power Reduction in Sequential Circuits
 IEEE Design and Test of Computers
, 1994
"... With the proliferation of portable devices and increasing levels of chip integration, reducing power consumption is becoming of paramount importance. We describe a technique to automatically synthesize gated clocks for finitestate machines (FSMs) to reduce power in the final implementation. This te ..."
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Cited by 24 (7 self)
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With the proliferation of portable devices and increasing levels of chip integration, reducing power consumption is becoming of paramount importance. We describe a technique to automatically synthesize gated clocks for finitestate machines (FSMs) to reduce power in the final implementation. This technique recognizes selfloops in the FSM (either from the state diagram or from a synchronous network) and uses the function described by the selfloops to gate the clock. The clock activation function is then used as don'tcare information to minimize the logic in the FSM for additional power savings. We applied these techniques to standard MCNC benchmarks and found an average reduction in power dissipation of 25%, at the cost of a 5% increase in area. 1 Introduction As portable devices proliferate and device sizes continue to shrink, allowing more devices to fit on a chip, power consumption has taken on increased importance. Much recent work has focused on accurate estimation of power co...
Delay Minimization for ZeroSkew Routing
 Proc. IEEE Intl. Conf. ComputerAided Design
, 1993
"... Delay minimization methods are proposed for zeroskew routings. A delaytime estimation formula is derived, which can be used as an objective function to be minimized in zeroskew routing algorithms. Moreover, the optimum wire width is formulated. Experimental results show that our methods with a cl ..."
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Cited by 18 (1 self)
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Delay minimization methods are proposed for zeroskew routings. A delaytime estimation formula is derived, which can be used as an objective function to be minimized in zeroskew routing algorithms. Moreover, the optimum wire width is formulated. Experimental results show that our methods with a clusteringbased algorithm achieve 50% reduction of the delay time on benchmark data with 3000 pins. 1 Department of Computer Science, Princeton University and C&C Systems Research Laboratories, NEC Corporation 1 Introduction With the increase of the clock rate in VLSI, the clocknet routing scheme plays more critical roles. In order to make the clock rate higher, at least two factors should be taken into account in clocknet routing. First, since the clock skew affects the clock period directly, exact zero skew is desired. Next, the delay time should be minimized in a clock net. Consider an example of singlephase clocking in Fig. 1. In CMOS design, the delay time is dominated by the rise/f...