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34
Principles and methods of Testing Finite State Machines a survey. The
 Proceedings of IEEE
, 1996
"... With advanced computer technology, systems are getting larger to fulfill more complicated tasks, however, they are also becoming less reliable. Consequently, testing is an indispensable part of system design and implementation; yet it has proved to be a formidable task for complex systems. This moti ..."
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Cited by 248 (13 self)
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With advanced computer technology, systems are getting larger to fulfill more complicated tasks, however, they are also becoming less reliable. Consequently, testing is an indispensable part of system design and implementation; yet it has proved to be a formidable task for complex systems. This motivates the study of testing finite state machines to ensure the correct functioning of systems and to discover aspects of their behavior. A finite state machine contains a finite number of states and produces outputs on state transitions after receiving inputs. Finite state machines are widely used to model systems in diverse areas, including sequential circuits, certain types of programs, and, more recently, communication protocols. In a testing problem we have a machine about which we lack some information; we would like to deduce this information by providing a sequence of inputs to the machine and observing the outputs produced. Because of its practical importance and theoretical interest, the problem of testing finite state machines has been studied in different areas and at various times. The earliest published literature on this topic dates back to the 50’s. Activities in the 60’s and early 70’s were motivated mainly by automata theory and sequential circuit testing. The area seemed to have mostly died down until a few years ago when the testing problem was resurrected and is now being studied anew due to its applications to conformance testing of communication protocols. While some old problems which had been open for decades were resolved recently, new concepts and more intriguing problems from new applications emerge. We review the fundamental problems in testing finite state machines and techniques for solving these problems, tracing progress in the area from its inception to the present and the state of the art. In addition, we discuss extensions of finite state machines and some other topics related to testing. 21.
Automated Unique Input Output sequence generation for conformance testing of FSMs
 The Computer Journal
, 2006
"... This paper describes a method for automatically generating unique input output (UIO) sequences for FSM conformance testing. UIOs are used in conformance testing to verify the end state of a transition sequence. UIO sequence generation is represented as a search problem and genetic algorithms are use ..."
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Cited by 20 (11 self)
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This paper describes a method for automatically generating unique input output (UIO) sequences for FSM conformance testing. UIOs are used in conformance testing to verify the end state of a transition sequence. UIO sequence generation is represented as a search problem and genetic algorithms are used to search this space. Empirical evidence indicates that the proposed method yields considerably better (up to 62 % better) results compared with random UIO sequence generation.
Computing unique input/output sequences using genetic algorithms
 In Proceedings of the 3rd International Workshop on Formal Approaches to Testing of Software (FATES’2003), volume 2931 of LNCS
, 2004
"... The problem of computing Unique Input/Ouput sequences(UIOs) is NPhard. Genetic algorithms (GAs) have been proven to be effective in providing good solutions for some NPhard problems. In this work, we investigated the construction of UIOs using GAs. We defined a fitness function to guide the search ..."
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Cited by 16 (7 self)
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The problem of computing Unique Input/Ouput sequences(UIOs) is NPhard. Genetic algorithms (GAs) have been proven to be effective in providing good solutions for some NPhard problems. In this work, we investigated the construction of UIOs using GAs. We defined a fitness function to guide the search of potential UIOs and introduce a DO NOT CARE character to improve the GA’s diversity. Experimental results suggest that, in a small system, the performance of the GA based approaches is no worse than that of random search while, in a more complex system, the GA based approaches outperform random search.
Testing from a finite state machine: extending invertibility to sequences
 THE COMPUTER JOURNAL
, 1997
"... When testing a system modelled as a finite state machine it is desirable to minimize the effort required. Yang and Ural [1990] demonstrate that it is possible to utilize test sequence overlap in order to reduce the test effort and Hierons [1996] represents this overlap by using invertible transition ..."
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Cited by 15 (10 self)
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When testing a system modelled as a finite state machine it is desirable to minimize the effort required. Yang and Ural [1990] demonstrate that it is possible to utilize test sequence overlap in order to reduce the test effort and Hierons [1996] represents this overlap by using invertible transitions. In this paper invertibility will be extended to sequences in order to further reduce the test effort and encapsulate a more general type of test sequence overlap. It will also be shown that certain properties of invertible sequences can be used in the generation of state identification sequences.
Testing protocols modeled as FSMs with timing parameters
, 1999
"... An optimization method is introduced for generating minimumlength test sequences taking into account timing constraints for FSM models of communication protocols. Due to active timers in many of today's protocols, the number of consecutive selfloops that can be traversed in a given state befo ..."
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Cited by 12 (7 self)
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An optimization method is introduced for generating minimumlength test sequences taking into account timing constraints for FSM models of communication protocols. Due to active timers in many of today's protocols, the number of consecutive selfloops that can be traversed in a given state before a timeout occurs is limited. A test sequence that does not consider timing constraints will likely be unrealizable in a test laboratory, thereby potentially resulting in the incorrect failing Z. of valid implementations or, vice versa . The solution uses a series of augmentations for a protocol's directed graph representation. The resulting test sequence is proven to be of minimumlength while not exceeding the tolerable limit of consecutive selfloops at each state. Although UIO sequences are used for state verification method, the results also are applicable to test generation that uses distinguishing or characterizing sequences.
MinimumCost Solutions for Testing Protocols with Timers
, 1997
"... A method to generate a minimumcost test sequence for a protocol with timers is presented. The protocol timers limit the number of consecutive selfloops that can be realized in a given state. The solution presented is applicable to test sequences that use any state identification method such as UIO ..."
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Cited by 10 (9 self)
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A method to generate a minimumcost test sequence for a protocol with timers is presented. The protocol timers limit the number of consecutive selfloops that can be realized in a given state. The solution presented is applicable to test sequences that use any state identification method such as UIO sequences, distinguishing sequences, and characterizing sequences. If valid and inopportune transition testing are combined, or if only valid transitions are considered, a minimumcost solution exists. In the case of testing inopportune transitions separately, however, finding a minimumcost solution is shown to be NPhard.
Transformation of Estelle modules aiming at test case generation
, 1995
"... This paper presents a method for transforming an extended finite state machine (EFSM) given as an Estelle normal form module into an equivalent expanded EFSM without control variables, i.e. an Estelle normal form module free of providedclauses. The transformed EFSM allows to apply methods based on ..."
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Cited by 8 (2 self)
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This paper presents a method for transforming an extended finite state machine (EFSM) given as an Estelle normal form module into an equivalent expanded EFSM without control variables, i.e. an Estelle normal form module free of providedclauses. The transformed EFSM allows to apply methods based on the finite state machine (FSM) model for test case generation. Using this approach, it is possible to cope with test sequence generation for control and data flow and with test data selection. The transformation is feasible if the variables that occur in providedclauses have finite, countable domains. For realistic protocol specifications, this condition is fulfilled most of the time.
A Technique to Generate Feasible Tests for Communications Systems with Multiple Timers
 IEEE/ACM TRANS. NETW
, 2003
"... We present a new model for testing realtime protocols with multiple timers, which captures complex timing dependencies by using simple linear expressions involving timerrelated variables. This new modeling technique, combined with the algorithms to eliminate inconsistencies, allows generation of fe ..."
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Cited by 7 (3 self)
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We present a new model for testing realtime protocols with multiple timers, which captures complex timing dependencies by using simple linear expressions involving timerrelated variables. This new modeling technique, combined with the algorithms to eliminate inconsistencies, allows generation of feasible test sequences without compromising their fault coverage. The model is specifically designed for testing to avoid performing full reachability analysis, and to control the growth of the number of test scenarios. Based on extended finite state machines, it is applicable to languages such as SDL, VHDL, and Estelle. The technique models a realistic testing framework in which each I/O exchange takes a certain time to realize and timers can be arbitrarily started or stopped. A software tool implementing this technique is used to generate test cases for the US Army wireless standard MILSTD 188220.
Separating sequence overlap for automated test sequence generation
 Autom. Softw. Eng
, 2006
"... Finite state machines have been used to model a number of classes of system and there has thus been much interest in the automatic generation of test sequences from finite state machines. Many finite state machine based test techniques utilize sequences that check the final states of transitions, th ..."
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Cited by 4 (2 self)
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Finite state machines have been used to model a number of classes of system and there has thus been much interest in the automatic generation of test sequences from finite state machines. Many finite state machine based test techniques utilize sequences that check the final states of transitions, the most general such sequence being a separating sequence: an input sequence that distinguishes between two states of an FSM. When using such techniques the test sequence length can be reduced by utilizing overlap. This paper investigates overlap for separating sequences and shows how this can be incorporated into test sequence generation.