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A HighPerformance Reconfigurable Elliptic Curve Processor for GF(2 m )
, 2000
"... . This work proposes a processor architecture for elliptic curves cryptosystems over fields GF(2 m ). This is a scalable architecture in terms of area and speed that exploits the abilities of reconfigurable hardware to deliver optimized circuitry for different elliptic curves and finite fields. ..."
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Cited by 68 (6 self)
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. This work proposes a processor architecture for elliptic curves cryptosystems over fields GF(2 m ). This is a scalable architecture in terms of area and speed that exploits the abilities of reconfigurable hardware to deliver optimized circuitry for different elliptic curves and finite fields. The main features of this architecture are the use of an optimized bitparallel squarer, a digitserial multiplier, and two programmable processors. Through reconfiguration, the squarer and the multiplier architectures can be optimized for any field order or field polynomial. The multiplier performance can also be scaled according to system's needs. Our results show that implementations of this architecture executing the projective coordinates version of the Montgomery scalar multiplication algorithm can compute elliptic curve scalar multiplications with arbitrary points in 0.21 msec in the field GF(2 167 ). A result that is at least 19 times faster than documented hardware imple...
An EnergyEfficient Reconfigurable PublicKey Cryptography Processor
 IEEE Journal of SolidState Circuits
, 2001
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A Scalable GF(p) Elliptic Curve Processor Architecture for Programmable Hardware
"... This work proposes a new elliptic curve processor architecture for the computation of point multiplication for curves defined over fields GF (p). This is a scalable architecture in terms of area and speed specially suited for memoryrich hardware platforms such a field programmable gate arrays ( ..."
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Cited by 20 (2 self)
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This work proposes a new elliptic curve processor architecture for the computation of point multiplication for curves defined over fields GF (p). This is a scalable architecture in terms of area and speed specially suited for memoryrich hardware platforms such a field programmable gate arrays (FPGAs). This processor uses a new type of highradix Montgomery multiplier that relies on the precomputation of frequently used values and on the use of multiple processing engines.
Modular exponentiation on reconfigurable hardware
 ECE Dept., Worcester Polytechnic Institute
, 1999
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A microcoded elliptic curve processor using FPGA technology
 IEEE Transactions on VLSI Systems
, 2002
"... Abstract—The implementation of a microcoded elliptic curve processor using fieldprogrammable gate array technology is described. This processor implements optimal normal basis field operations in P. The design is synthesized by a parameterized module generator, which can accommodate arbitrary and a ..."
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Cited by 17 (0 self)
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Abstract—The implementation of a microcoded elliptic curve processor using fieldprogrammable gate array technology is described. This processor implements optimal normal basis field operations in P. The design is synthesized by a parameterized module generator, which can accommodate arbitrary and also produce field multipliers with different speed/area tradeoffs. The control part of the processor is microcoded, enabling curve operations to be incorporated into the processor and hence reducing the chip’s I/O requirements. The microcoded approach also facilitates rapid development and algorithmic optimization: for example, projective and affine coordinates were supported using different microcode. The design was successfully tested on a Xilinx Virtex XCV10006 device and could perform an elliptic curve multiplication over the field P using affine and projective coordinates for aIIQISS and IUQ. Index Terms—Arithmetic, cryptography, Galois fields, microprogramming, public key cryptography, reconfigurable architectures. I.
A SuperSerial Galois Fields Multiplier for FPGAs and its Application to PublicKey Algorithms
 In Seventh Annual IEEE Symposium on FieldProgrammable Custom Computing Machines, FCCM '99
, 1999
"... This contribution introduces a scalable multiplier architecture for Galois field GF (2 k ) amenable for field programmable gate arrays (FPGAs) implementations. This architecture is well suited for the implementation of publickey cryptosystems which require programmable multipliers in large Galois ..."
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Cited by 12 (2 self)
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This contribution introduces a scalable multiplier architecture for Galois field GF (2 k ) amenable for field programmable gate arrays (FPGAs) implementations. This architecture is well suited for the implementation of publickey cryptosystems which require programmable multipliers in large Galois fields. The architecture trades a reduction in resources with an increase in the number of clock cycles. This architecture is also fine grain scalable in both the time and the area (or logic) dimensions thus facilitating implementations that maximize their use of finite FPGA resources while achieving fast computational speed. This leads to an architecture that requires less resources than traditional bit serial multipliers, which we demonstrated with implementations of multipliers in the field GF (2 167 ). Our results demonstrate that for this field one can realize superserial multipliers that use 2.76 times fewer function generators and 6.84 times fewer flipflops than their serial mult...
Customizable elliptic curve cryptosystems
 IEEE Transactions on Very Large Scale Integration (VLSI) Systems
, 2005
"... Abstract—This paper presents a method for producing hardware designs for elliptic curve cryptography (ECC) systems over the finite field qp@P A, using the optimal normal basis for the representation of numbers. Our field multiplier design is based on a parallel architecture containing multiplebit s ..."
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Cited by 11 (1 self)
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Abstract—This paper presents a method for producing hardware designs for elliptic curve cryptography (ECC) systems over the finite field qp@P A, using the optimal normal basis for the representation of numbers. Our field multiplier design is based on a parallel architecture containing multiplebit serial multipliers; by changing the number of such serial multipliers, designers can obtain implementations with different tradeoffs in speed, size and level of security. A design generator has been developed which can automatically produce a customised ECC hardware design that meets userdefined requirements. To facilitate performance characterization, we have developed a parametric model for estimating the number of cycles for our generic ECC architecture. The resulting hardware implementations are among the fastest reported: for a key size of 270 bits, a point multiplication in a Xilinx XC2V6000 FPGA at 35 MHz can run over 1000 times faster
Elliptic & hyperelliptic curves on embedded µp
 ACM Transactions in Embedded Computing Systems (TECS), 2003. Special Issue on Embedded Systems and Security
"... To appear in the special issue on Embedded Systems and Security of the ..."
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Cited by 10 (4 self)
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To appear in the special issue on Embedded Systems and Security of the
High Performance Elliptic Curve Cryptographic Coprocessor
, 2003
"... In FIPS 1862, NIST recommends several finite fields to be used in the elliptic curve digital signature algorithm (ECDSA). Of the ten recommended finite fields, five are binary extension fields with degrees ranging from 163 to 571. The fundamental building block of the ECDSA, like any ECC based prot ..."
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Cited by 8 (2 self)
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In FIPS 1862, NIST recommends several finite fields to be used in the elliptic curve digital signature algorithm (ECDSA). Of the ten recommended finite fields, five are binary extension fields with degrees ranging from 163 to 571. The fundamental building block of the ECDSA, like any ECC based protocol, is elliptic curve scalar multiplication. This operation is also the most computationally intensive. In many situations it may be desirable to accelerate the elliptic curve scalar multiplication with specialized hardware.
Hardware/software CoDesign Of An Elliptic Curve PublicKey Cryptosystem
 In Proceedings IEEE Workshop on of Signal Processing Systems
, 2001
"... This contribution discusses an implementation of an elliptic curve publickey cryptosystem on the Atmel FPSLIC, a system on a chip (SOC) that integrates a 40K FPGA with an AVR microcontroller and a set of peripherals. The FPGA is ideally suited for an efficient implementation of the underlying finit ..."
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Cited by 7 (3 self)
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This contribution discusses an implementation of an elliptic curve publickey cryptosystem on the Atmel FPSLIC, a system on a chip (SOC) that integrates a 40K FPGA with an AVR microcontroller and a set of peripherals. The FPGA is ideally suited for an efficient implementation of the underlying finite field arkhmetic. The software benefits the global control. We use a standard basis represent.tion for the field elements and projective coordinates to implement the group operation. The results for area are comparable with existing hardware implementations. Although no attempts have been made yet to reduce the critical path delay of the hardware part, we obtained promising results towards speed and throughput. A clock frequency of 10 MHz is realized, but a lot more nmst be possible after optimization.