This paper is an in-depth review on silicon implementations of threshold logic gates that covers several decades. In this paper, we will mention early MOS threshold logic solutions and detail numerous very-large-scale integration (VLSI) implementations including capacitive (switched capacitor and floating gate with their variations), conductance/current (pseudo-nMOS and output-wired-inverters, including a plethora of solutions evolved from them), as well as many differential solutions. At the end, we will briefly mention other implementations, e.g., based on negative resistance devices and on single electron technologies.

In this paper, we explore the potential of bus interconnection models using the Multiple-Valued Logic paradigm to reduce the power consumption of on-chip address and data buses within embedded SoC platforms. Data is sent over the buses using radix-r number system, i.e. ternary, balanced ternary or quaternary, rather than binary. This allows more compact bus design with less number of bus lines. Reducing the number of bus lines also allows us to increase the distance between the adjacent bus lines using the same silicon area. This further reduces interwire capacitance and may lead to significant onchip bus power reduction for embedded SoCs designed with deep sub-micron technology. We also analyze the bus switching activity on on-chip address and data buses operating in radix-r number system, and observe that the number of bus transitions in a radix-r bus, particularly in a quaternary bus, is significantly less than the number of bus transitions in a binary bus. Thus, this results in significant power savings in the total on-chip bus power. Our experimental results show that the radix-r bus models replacing 32-bit binary equivalent can provide up to 61 % reduction in the address bus power and up to 58 % reduction in the data bus power when compared to a binary bus model. Thus, on-chip radix-r bus models can be alternative to the binary one in power-efficient embedded systems. 1.

Power optimization in current mode circuits We propose a method to minimize power dissipation in current-mode CMOS analog and multiple-valued logic (MVL) circuits employing a stack of current comparators. First, we present an approximation model for current in a current comparator circuit. Power reduction is achieved through turning off the redundant comparator circuits using a switch-architecture. Simulations are carriedout for current-mode flash ADC designs and literal generating circuits for MVL. We show that the simple switch architecture with minimum area overhead can be used to trade-off power dissipation with delay in these designs. 1.

In this paper we present a model for diagnosis of errors in Sequential Multi-Valued Logic Networks (SMVLN). The method allows not only to detect errors in an implementation, but also identifies the fault location. In contrast to many previously presented approaches this model does not consider a specific implementation. Instead the model assumes tests based on the transition behavior of the corresponding MVL Finite State Machine (FSM) on the functional level. We present a method for constructing a minimal cost test based on AND/OR graphs using tests with MV outcomes. The model enables encoding over twovalued circuits as well as consideration of SMVLNs. The new approach provides efficient solution even for large MVL FSMs with up to 50000 states. Experimental results for randomly generated FSMs are given that demonstrate the efficiency of our approach. 1 Introduction Several circuit design methods for Multi-Valued Logic (MVL) have been proposed in the past few years [3, 6]. These new ...

This paper proposes two bounded arithmetic operations, which are easily realized with current signals. Based on these two operations, a bounded algebra system suitable for describing current-mode digital circuits is developed and its relationship to the Boolean Algebra, which is suitable for representing voltage-mode digital circuits, is investigated.

In this paper, we propose three novel cache models using Multiple-Valued Logic (MVL) paradigm to reduce the cache data storage area and cache energy consumption for embedded systems. Multiple-valued caches have significant potential for compact and powerefficient cache array design. The cache models differ from each other depending on whether they store tag and data in binary, radix-r or a mix of both. Our analytical study of cache silicon area shows that an embedded System-on-achip (SoC) equipped with a multiple-valued cache model can reduce the cache data storage area up to 6% regardless of cache parameters. Also, our experiments on several embedded benchmarks demonstrate that dynamic cache energy consumption can be reduced up to 62 % in a multiple-valued instruction cache in an embedded SoC. 1.