Abstract not found

Minimizing power consumption continues to grow as a critical design issue for many platforms, from embedded systems to CMPs to ultrascale parallel systems. As growing cache sizes consume larger portions of the die, leakage current becomes an increasingly important component in overall power. Since most cache lines remain idle most of the time, drowsy caching techniques that reduce voltages on selected lines can reduce this leakage power. Most drowsy caching policies in the literature update drowsy/non-drowsy state after a given execution window: e.g., the widely used simple policy puts all caches lines to sleep after a specified number of clock cycles. Such methods are inherently architecturespecific. We instead introduce a drowsy caching mechanism

We evaluate the leakage reduction for both instruction and data cache in presence of drowsy or decay techniques. We discovered that a filter cache, traditionally used for reducing active power, can help reduce also leakage. The key idea is to reduce the lifetime of the lines that are in high-power state inside a leakage-saving cache. Power consumption has become one of the main concerns for designers, together with the performance. Caches account for the largest fraction of on-chip transistors in most modern processors. Therefore, they are a primary candidate for attacking the problem of the leakage. In average with the proposed solution, for instruction cache 24 % improvement in leakage savings and 1.5 % in IPC (Instruction Per Cycle) can be achieved with respect to drowsy cache. For data caches, 5 % and 5.4 % improvement can be achieved respectively. Experiments have been performed also with decay cache showing fewer benefits.