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Using Contrapositive Law in an Implication Graph to Identify Logic Redundancies
 Proc. 18 th International Conf. VLSI Design
, 2005
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Theorems on Redundancy Identification
, 2003
"... There is a class of implicationbased methods that identify logic redundancy from circuit topology and without any primary input assignment. These methods are less complex than automatic test pattern generation (ATPG) but identify only a subset of all redundancies. This paper provides new results to ..."
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There is a class of implicationbased methods that identify logic redundancy from circuit topology and without any primary input assignment. These methods are less complex than automatic test pattern generation (ATPG) but identify only a subset of all redundancies. This paper provides new results to enlarge this subset. Contributions are a fixedvalue theorem and two theorems on fanout stem unobservability. Our framework is an implication graph of signal controllabilities and observabilities represented as Boolean variables. Besides the conventional implication edges this graph also contains partial implications implemented by AND nodes. An analysis of the transitive closure (TC) of this graph provides many redundancies. Weaknesses of this procedure are in dealing with the effects of xedvalued variables on TC and the lack of observability relations across fanouts. The fixedvalue theorem adds unconditional edges from all variables to the fixed variable and then recomputes TC recursively until no new fixed nodes are found. The stem unobservability theorems determine the observability status of a fanout stem from its dominator set, which either has fixed values or is unobservable. Results are considerably improved from the previously reported implicationbased identi ers. In the c5315 circuit we identify 58 out of 59 redundant faults. All 34 redundant faults of c6288 are identi ed. Besides, our procedure can classify faults according to the causes of their redundancy, namely, unexcitable, unobservable, or undrivable. For the future research, we provide examples of cases where the present method still fails.
Using Contrapositives to Enhance the Implication Graph of Logic Circuits
 in Proc. of the 13 th IEEE North Atalantic Test Workshop
, 2004
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Diagnostic and Detection Fault Collapsing for Multiple Output Circuits
"... We discuss fault equivalence and dominance relations for multiple output combinational circuits. The conventional definition for equivalence says that “Two faults are equivalent if and only if the corresponding faulty circuits have identical output functions”. This definition, which is based on indi ..."
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We discuss fault equivalence and dominance relations for multiple output combinational circuits. The conventional definition for equivalence says that “Two faults are equivalent if and only if the corresponding faulty circuits have identical output functions”. This definition, which is based on indistinguishability of the faults, is extended for multiple output circuits as “Two faults of a Boolean circuit are equivalent if and only if the pair of the output functions is identical at each output of the circuit”. This is termed as diagnostic equivalence in this paper. “If all tests that detect a fault also detect another fault, not necessarily on the same output, then the two faults are called detection equivalent”. Two detection equivalent faults need not be indistinguishable. The definitions for fault dominance follow on similar lines. A novel algorithm based on redundancy identification has been proposed to find the equivalence and dominance collapsed sets based on diagnostic and detection collapsing. Applying the algorithm to a 4bit ALU would collapse the total fault set of 502 faults to 253 and 155, respectively, according to diagnostic equivalence and dominance. The collapsed sets have 234 and 92 faults, respectively, for detection equivalence and dominance. In comparison, the traditional structural equivalence and dominance collapsing results in 301 and 248 faults, respectively. Finally, we use librarybased functional collapsing in a hierarchical system and find that smaller fault sets are obtained with an order of magnitude reduction in CPU time for very large circuits. 1.
Fault Nodes in Implication Graph for Equivalence/Dominance Collapsing, and Identifying Untestable and Independent Faults Abstract
"... This paper presents a new fault node for implication graph that represents the Boolean detectability status of a fault in the circuit. An implication graph with fault nodes is termed functional fault graph (FFG) because such a graph stores both the functional information and the fault information of ..."
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This paper presents a new fault node for implication graph that represents the Boolean detectability status of a fault in the circuit. An implication graph with fault nodes is termed functional fault graph (FFG) because such a graph stores both the functional information and the fault information of the circuit. By computing the transitive closure and graph condensation of the FFG of a circuit, we show that we can collapse faults, and identify untestable faults and independent fault pairs in the circuit. Compared to prior fault independentbased approaches for fault collapsing, our technique gives the best result by reducing the faultset size by 66%. Additional advantages of our technique compared to previous techniques are: a) It can also identify independent fault pairs in the circuit, and b) It can be extended for other fault models and has a variety of applications. Our experiment with c7552 also found more than 268K independent fault pairs. This work also introduces the first faultindependent polynomialtime approach for identifying untestable transition delay faults. 1
iii
, 2005
"... Except where reference is made to the work of others, the work described in this thesis is my own or was done in collaboration with my advisory committee. This thesis does not include proprietary or classified information. Certificate of Approval: ..."
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Except where reference is made to the work of others, the work described in this thesis is my own or was done in collaboration with my advisory committee. This thesis does not include proprietary or classified information. Certificate of Approval:
FixedValue and Stem Unobservability Theorems for Logic Redundancy Identification
, 2003
"... There is a class of implicationbased methods that identify logic redundancy from circuit topology and without any primary input assignment. These methods are less complex than automatic test pattern generation (ATPG) but identify only a subset of all redundancies. This paper provides new results to ..."
Abstract
 Add to MetaCart
There is a class of implicationbased methods that identify logic redundancy from circuit topology and without any primary input assignment. These methods are less complex than automatic test pattern generation (ATPG) but identify only a subset of all redundancies. This paper provides new results to enlarge this subset. Contributions are a fixedvalue theorem and two theorems on fanout stem unobservability. We represent signal controllabilities and observabilities using an implication graph and its transitive closure (TC). Both complete and partial implications are included. Weaknesses of this procedure areindealing with the e ects of xedvalued variables on TC and the lack of observability relations across fanouts. The xedvalue theorem adds unconditional edges from all variables to the xed variable and then recomputes TC recursively until no new fixed nodes are found. The stem unobservability theorems determine the observability status of a fanout stem from its dominator set, which either has fixed values, or is unobservable. Results are considerably improved from the previously reported implicationbased identi ers. In the c5315 circuit we identify 58 out of 59 redundant faults. All 34 redundant faults of c6288 are identified.