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Multilevel fullchip routing with testability and yield enhancement
 Proc. SLIP
, 2005
"... We propose in this paper a multilevel fullchip routing algorithm that improves testability and diagnosability, manufacturability, and signal integrity for yield enhancement. Two major issues are addressed. (1) The oscillation ring (OR) test and its diagnosis scheme for interconnect based on the pop ..."
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Cited by 5 (3 self)
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We propose in this paper a multilevel fullchip routing algorithm that improves testability and diagnosability, manufacturability, and signal integrity for yield enhancement. Two major issues are addressed. (1) The oscillation ring (OR) test and its diagnosis scheme for interconnect based on the popular IEEE P1500 are integrated into the multilevel routing framework to achieve testability enhancement. We augment the traditional multilevel framework of coarsening followed by uncoarsening by introducing a preprocessing stage that analyzes the oscillation ring structure for better resource estimation before the coarsening stage, and a final stage after uncoarsening that improves testability to achieve 100 % interconnect fault coverage and maximal diagnosability. (2) We present a heuristic to balance routing congestion to optimize the multiplefault probability, chemical mechanic polishing (CMP) and optical proximity correction (OPC) induced manufacturability, and crosstalk effects, for yield improvement. Experimental results on the MCNC benchmark circuits show that the proposed OR method achieves 100 % fault coverage and the maximal diagnosis resolution for interconnects, and the multilevel routing algorithm effectively balances the routing density to achieve 100 % routing completion. Compared with [24], the experimental results show that our router improves the maximal congestion by 1.24X6.11X in runtime speedup by 1.08X7.66X, and improves the average congestion by 1.00X4.52X with the improved congestion deviation by 1.37X5.55X. 1.
Yield Analysis and Optimization
"... In this chapter, we are going to discuss yield loss mechanisms, yield analysis and common physical design methods to improve yield. Yield is defined as the ratio of the number of products that can be sold to the number of products that can be manufactured. Estimated typical cost of modern 300mm or 1 ..."
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Cited by 3 (0 self)
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In this chapter, we are going to discuss yield loss mechanisms, yield analysis and common physical design methods to improve yield. Yield is defined as the ratio of the number of products that can be sold to the number of products that can be manufactured. Estimated typical cost of modern 300mm or 12inch wafer 0.13 µm process fabrication plant is $24 billion. Typical number of processing steps for a modern integrated circuit is more than 150. Typical production cycletime is over 6 weeks. Individual wafers cost multiple thousands of dollars. Given such huge investments, consistent high yield is necessary for faster time to profit. 1
Synergistic Physical Synthesis for Manufacturability and Variability in 45nm Designs and Beyond
"... Nanometer IC designs are increasingly challenged by manufacturing closure, i.e., being fabricated with high product yield, mainly due to aggressive technology scaling and increasing process/environmental variations. Realizing the criticality of addressing manufacturability for higher yield and toler ..."
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Cited by 2 (2 self)
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Nanometer IC designs are increasingly challenged by manufacturing closure, i.e., being fabricated with high product yield, mainly due to aggressive technology scaling and increasing process/environmental variations. Realizing the criticality of addressing manufacturability for higher yield and tolerance to variations during design, there has been a surge of research activities recently from both academia and industry. In this paper, we will survey the key activities in synergistic physical synthesis and shed lights on some of the future research directions.
Track Routing and Optimization for Yield
"... Abstract—In this paper, we propose track routing and optimization for yield (TROY), the first track router for the optimization of yield loss due to random defects. As the probability of failure (POF), which is an integral of the critical area and the defect size distribution, strongly depends on wi ..."
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Abstract—In this paper, we propose track routing and optimization for yield (TROY), the first track router for the optimization of yield loss due to random defects. As the probability of failure (POF), which is an integral of the critical area and the defect size distribution, strongly depends on wire ordering, sizing, and spacing, track routing can play a key role in effective wire planning for yield optimization. However, a straightforward formulation of yielddriven track routing can be shown to be integer nonlinear programming, which is a nondeterministic polynomialtime complete problem. TROY overcomes the computational complexity by combining two effective techniques, i.e., the minimum Hamiltonian path (MHP) from graph theory and the secondorder cone programming (SOCP) from mathematical optimization. First, TROY performs wire ordering to minimize the critical area for short defects by finding an MHP. Then, TROY carries out optimal wire sizing/spacing through SOCP optimization based on the given wire order. Since the SOCP can be optimally solved in near linear time, TROY efficiently achieves globally optimal wire sizing/spacing for the minimal POF. Index Terms—Minimum Hamiltonian path (MHP), physical design, random defects, secondorder cone programming (SOCP), track routing, yield. I.
Netaware Critical Area extraction for VLSI opens via Voronoi diagrams
"... We address the problem of computing critical area for opens in a circuit layout in the presence of loops and redundant interconnects. The extraction of critical area is the main computational problem in VLSI yield prediction for random manufacturing defects. Our approach first models the problem as ..."
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We address the problem of computing critical area for opens in a circuit layout in the presence of loops and redundant interconnects. The extraction of critical area is the main computational problem in VLSI yield prediction for random manufacturing defects. Our approach first models the problem as a graph problem and solves it efficiently by exploiting its geometric nature. The approach expands the Voronoi critical area computation paradigm [10, 7] with the ability to accurately compute critical area for missing material defects in a netaware fashion. Generalized Voronoi diagrams used in the solution are combinatorial structures of independent interest. 1
THE HIGHER ORDER HAUSDORFF VORONOI DIAGRAM AND VLSI CRITICAL AREA EXTRACTION FOR VIABLOCKS
"... the ability to accurately compute critical area for viablocks on via and contact layers in the presence of multilayer loops, redundant vias, and redundant interconnects. Critical area is a measure reflecting the sensitivity of a VLSI design to random defects during IC manufacturing. The method is ..."
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the ability to accurately compute critical area for viablocks on via and contact layers in the presence of multilayer loops, redundant vias, and redundant interconnects. Critical area is a measure reflecting the sensitivity of a VLSI design to random defects during IC manufacturing. The method is based on concepts of the higher order Hausdorff Voronoi diagram of point clusters in the plane. We investigate structural properties of the orderk Hausdorff Voronoi diagram and present a simple iterative approach that computes the ordinary Hausdorff Voronoi diagram of iteratively determined clusters of points. We highlight simplifications in the L ∞ metric, a metric of practical interest in VLSI critical area extraction.
Approved by: FAST INTERCONNECT OPTIMIZATION
, 2005
"... As the continuous trend of Very Large Scale Integration (VLSI) circuits technology scaling and frequency increases, delay optimization techniques for interconnect are increasingly important for achieving timing closure of high performance designs. For the gigahertz microprocessor and multimillion ..."
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As the continuous trend of Very Large Scale Integration (VLSI) circuits technology scaling and frequency increases, delay optimization techniques for interconnect are increasingly important for achieving timing closure of high performance designs. For the gigahertz microprocessor and multimillion gate ASIC designs it is crucial to have fast algorithms in the design automation tools for many classical problems in the field to shorten time to market of the VLSI chip. This research presents algorithmic techniques and constructive models for two such problems: (1) Fast buffer insertion for delay optimization, (2) Wire sizing for delay optimization and variation minimization on nontree networks. For the buffer insertion problem, this dissertation proposes several innovative speedup techniques for different problem formulations and the realistic requirement. For the basic buffer insertion problem, an O(n log 2 n) optimal algorithm that runs much faster than the previous classical van Ginneken’s O(n 2) algorithm is proposed, where n is the number of buffer positions. For modern design libraries that contain hundreds of buffers, this research also proposes an optimal algorithm in O(bn 2)time
Approved by: LAYOUT OPTIMIZATION IN ULTRA DEEP SUBMICRON VLSI DESIGN
, 2006
"... As fabrication technology keeps advancing, many deep submicron (DSM) effects have become increasingly evident and can no longer be ignored in Very Large Scale Integration (VLSI) design. In this dissertation, we study several deep submicron problems (eg. coupling capacitance, antenna effect and del ..."
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As fabrication technology keeps advancing, many deep submicron (DSM) effects have become increasingly evident and can no longer be ignored in Very Large Scale Integration (VLSI) design. In this dissertation, we study several deep submicron problems (eg. coupling capacitance, antenna effect and delay variation) and propose optimization techniques to mitigate these DSM effects in the placeandroute stage of VLSI physical design. The placeandroute stage of physical design can be further divided into several steps: (1) Placement, (2) Global routing, (3) Layer assignment, (4) Track assignment, and (5) Detailed routing. Among them, layer/track assignment assigns major trunks of wire segments to specific layers/tracks in order to guide the underlying detailed router. In this dissertation, we have proposed techniques to handle coupling capacitance at the layer/track assignment stage, antenna effect at the layer assignment, and delay variation at the ECO (Engineering Change Order) placement stage, respectively. More specifically, at layer assignment, we have proposed an improved probabilistic model to quickly estimate the amount of coupling capacitance for timing optimization. Antenna effects are also handled at layer assignment through a lineartime tree partitioning algorithm. At the track assignment stage, timing is