Results 1  10
of
15
Dualvdd interconnect with chiplevel time slack allocation for FPGA power reduction
, 2006
"... To reduce FPGA power, Vdd programmability has been proposed recently to select Vddlevel for interconnects and to powergate unused interconnects. However, Vddlevel converters used in the existing Vddprogrammable method consume a large amount of leakage. In this paper, we propose two ways to avoid ..."
Abstract

Cited by 8 (3 self)
 Add to MetaCart
(Show Context)
To reduce FPGA power, Vdd programmability has been proposed recently to select Vddlevel for interconnects and to powergate unused interconnects. However, Vddlevel converters used in the existing Vddprogrammable method consume a large amount of leakage. In this paper, we propose two ways to avoid using level converters in interconnects, tree based level converter insertion (TLC) and dualVdd tree based level converter insertion (dTLC). TLC enforces that there is only one Vddlevel within each routing tree while dTLC can have different Vddlevels within a routing tree, but no VddL switch drives VddH switches. We develop dualVdd assignment algorithms considering chiplevel time slack allocation for maximum power reduction. Our algorithms include TLCS and dTLCS, power sensitivity based algorithms with implicit time slack allocation and dTLCLP, a linear programming (LP) based algorithm with explicit time slack allocation. All allocate time slack first to interconnects with higher power sensitivity and assign lowVdd to them for more power reduction. Experiments show that dTLCLP obtains the lowest power consumption. Compared to dTLCLP, dTLCS obtains slightly higher power consumption but runs 3X faster. Compared to the existing segmentbased level converter insertion (SLC) for dualVdd, dTLCLP reduces interconnect power by 52.90 % without performance loss for the MCNC benchmark circuits.
Simultaneous time slack budgeting and retiming for dualVdd FPGA power reduction
 in Proc. Design Automation Conf
, 2006
"... Field programmable dualVdd interconnects are effective to reduce FPGA power. Assuming uniform length interconnects, existing work has developed time slack budgeting to minimize power based on estimating the lower bound of power reduction using dualVdd for given time slack. In this paper, we show t ..."
Abstract

Cited by 6 (2 self)
 Add to MetaCart
(Show Context)
Field programmable dualVdd interconnects are effective to reduce FPGA power. Assuming uniform length interconnects, existing work has developed time slack budgeting to minimize power based on estimating the lower bound of power reduction using dualVdd for given time slack. In this paper, we show that such lower bound estimation cannot be extended to mixed length interconnects that are used in modern FPGAs. We develop a technique to estimate power reduction using dualVdd for mixed length interconnects, and apply linear programming (LP) to solve slack budgeting to minimize power for mixed length interconnects. Experiments show 53 % power reduction on average compared to singleVdd interconnects. Furthermore, this paper presents a simultaneous retiming and slack budgeting algorithm to reduce power in dualVdd FPGAs considering placement and flipflop binding constraints. The algorithm is based on mixed integer and linear programming (MILP) and achieves up to 20 % power reduction compared to retiming followed by slack budgeting. We propose a runtime efficient flow to apply simultaneous retiming and slack budgeting only when it is necessary. To the best of our knowledge, this paper is the first indepth study of simultaneous retiming and slack budgeting for dualVdd programmable FPGA power reduction while considering layout constraints.
Statistical DualVdd assignment for FPGA interconnect power reduction
 in Proc. Design Automation and Test in Europe
, 2007
"... Field programmable dualVdd interconnects are effective to reduce FPGA power. However, the deterministic Vdd assignment leverages timing slack exhaustively and significantly increases the number of nearcritical paths, which results in a degraded timing yield with process variation. In this paper, w ..."
Abstract

Cited by 2 (2 self)
 Add to MetaCart
(Show Context)
Field programmable dualVdd interconnects are effective to reduce FPGA power. However, the deterministic Vdd assignment leverages timing slack exhaustively and significantly increases the number of nearcritical paths, which results in a degraded timing yield with process variation. In this paper, we present two statistical Vdd assignment algorithms. The first greedy algorithm is based on sensitivity while the second one is based on timing slack budgeting. Both minimize chiplevel interconnect power without degrading timing yield. Evaluated with MCNC circuits, the statistical algorithms reduce interconnect power by 40 % compared to the singleVdd FPGA with power gating. In contrast, the deterministic algorithm reduces interconnect power by 51 % but degrades timing yield from 97.7 % to 87.5%. 1.
Field Programmability of Supply Voltages for FPGA Power Reduction
, 2007
"... Power reduction is of growing importance for fieldprogrammable gate arrays (FPGAs). In this paper, we apply programmable supply voltage (Vdd) to reduce FPGA power. We first design FPGA logic fabrics using dualVdd levels and show that fieldprogrammable power supply is required to obtain a satisfa ..."
Abstract

Cited by 2 (0 self)
 Add to MetaCart
Power reduction is of growing importance for fieldprogrammable gate arrays (FPGAs). In this paper, we apply programmable supply voltage (Vdd) to reduce FPGA power. We first design FPGA logic fabrics using dualVdd levels and show that fieldprogrammable power supply is required to obtain a satisfactory powerversusperformance tradeoff. We further design FPGA interconnect fabrics for finegrained Vdd programmability with minimal increase of the number of configuration staticrandomaccessmemory cells. With a simple yet practical computeraided design flow to leverage the fieldprogrammable dualVdd logic and interconnect fabrics, we carry out a highly quantitative study using placed and routed benchmark circuits, and delay, power, and area models obtained from detailed circuit designs. Compared to singleVdd FPGAs with the Vdd level suggested by the International Technology Roadmap for Semiconductors for 100nm technology, fieldprogrammable dualVdd FPGAs reduce the total power by 47.61 % and the energydelay product by 27.36%.
Design of poweraware FPGA fabrics
, 2007
"... We present two techniques to reduce the power consumption in FPGAs. The first technique uses two supply voltages: timingcritical paths run on normal Vdd, while the noncritical ones save power by using a lower Vdd. Our programmable dualVdd architectures and Vdd assignment algorithms provide an av ..."
Abstract
 Add to MetaCart
We present two techniques to reduce the power consumption in FPGAs. The first technique uses two supply voltages: timingcritical paths run on normal Vdd, while the noncritical ones save power by using a lower Vdd. Our programmable dualVdd architectures and Vdd assignment algorithms provide an average power saving of 61 % across the MCNC benchmarks. The second technique targets applications where configuration time is crucial. It uses Asymmetric SRAM (ASRAM) (instead of highVt SRAM) cells to implement the configuration memory. Our bitinversion algorithm further reduces leakage by increasing the number of ASRAM cells that are in their preferred state.
An Efficient Method for LargeScale Slack Allocation
, 2008
"... We consider a timing or project graph, with given delays on the edges and given arrival times at the source and sink nodes. We are to find the arrival times at the other nodes; these determine the timing slacks, which must be nonnegative, on the edges. The set of possible timing slacks is a polyhedr ..."
Abstract
 Add to MetaCart
We consider a timing or project graph, with given delays on the edges and given arrival times at the source and sink nodes. We are to find the arrival times at the other nodes; these determine the timing slacks, which must be nonnegative, on the edges. The set of possible timing slacks is a polyhedron; to choose one we maximize a separable concave utility function, such as the sum of the logarithms of the slacks. This slack allocation problem, for which we give a simple statistical interpretation, is convex, and can be solved by a variety of methods. Gradient and coordinate ascent methods are simple and scale to large problems, but can converge slowly, depending on the topology and problem data. The Newton method, in contrast, reliably computes an accurate solution, but typically cannot scale beyond problems with a few thousand nodes. In this paper we describe a custom truncated Newton method that efficiently computes an accurate solution, and scales to large graphs (say, with a million or more nodes). Our method typically requires just a few hundred iterations, with each iteration requiring a few passes over the graph; in particular, our method has approximately linear complexity in the size of the problem. The same approach can be used to solve slack allocation problems with constraints, using an interiorpoint method that relies on our custom truncated Newton approach.
44.1 Leakage Efficient ChipLevel DualVdd Assignment with Time Slack Allocation for FPGA Power Reduction ∗
"... To reduce power, Vdd programmability has been proposed recently to select Vddlevel for interconnects and to powergate unused interconnects. However, Vddlevel converters used in the Vddprogrammable method consume a large amount of leakage. In this paper, we develop chiplevel dualVdd assignment a ..."
Abstract
 Add to MetaCart
(Show Context)
To reduce power, Vdd programmability has been proposed recently to select Vddlevel for interconnects and to powergate unused interconnects. However, Vddlevel converters used in the Vddprogrammable method consume a large amount of leakage. In this paper, we develop chiplevel dualVdd assignment algorithms to guarantee that no lowVdd interconnect switch drives highVdd interconnect switches. This removes the need of Vddlevel converters and reduces interconnect leakage and interconnect device area by 91.78% and 25.48%, respectively. The assignment algorithms include power sensitivity based heuristics with implicit time slack allocation and a linear programming (LP) based method with explicit time slack allocation. Both first allocate time slack to interconnects with higher transition density and assign lowVdd to them for more power reduction. Compared to the aforementioned Vddprogrammable method using Vddlevel converters, the LP based algorithm reduces interconnect power by 65.13 % without performance loss for the MCNC benchmark circuits. Compared to the LP based algorithm, the sensitivity based heuristics can obtain slightly smaller power reduction but run 4X faster.
REDUCING POWER IN FPGA DESIGNS THROUGH GLITCH REDUCTION
, 2007
"... of a thesis submitted by ..."
(Show Context)
Power Optima l DualVdd Bu ffered Tre e Con sid erin g Bu f fer Stations and Blockages ∗
"... This paper presents the first indepth study on applying dual Vdd buffers to buffer insertion and multisink buffered tree construction for power minimization under delay constraint. To tackle the problem of dramatic complexity increment due to simultaneous delay and power consideration and increase ..."
Abstract
 Add to MetaCart
(Show Context)
This paper presents the first indepth study on applying dual Vdd buffers to buffer insertion and multisink buffered tree construction for power minimization under delay constraint. To tackle the problem of dramatic complexity increment due to simultaneous delay and power consideration and increased buffer choices, we develop a samplingbased subsolutions (i.e. options) propagation method and a balanced search treebased data structure for option pruning. We obtain 17x speedup with little loss of optimality compared to the exact option propagation. Moreover, compared to buffer insertion with single Vdd buffers, dualVdd buffers reduce power by 23 % at the minimum delay specification. In addition, compared to the delayoptimal tree using single Vdd buffers, our poweroptimal buffered tree reduces power by 7 % and 18 % at the minimum delay specification when single Vdd and dual Vdd buffers are used respectively.