Abstract: Increasing levels of integration and high speeds of operation have made the problem of testing complex systems-on-packages very difficult. Testing packages with multi-gigahertz RF and optical components is even more difficult as external tester costs tend to escalate rapidly beyond 3 GHz. The extent of the problem can be gauged by the fact that test cost is approaching almost 40 % of the total manufacturing cost of these packages. To alleviate test costs, various solutions relying on built-off test (BOT) and built-in test (BIT) of embedded high-speed components of SOPs have been developed. These migrate some of the external tester functions to the tester load board (BOT) and to the package and the die encapsulated in the package (BIT) in an “intelligent ” manner. This paper provides a discussion of the emerging BOT and BIT schemes for embedded high-speed RF/analog/mixed-signal circuits in SOPs. The pros and cons of each scheme are discussed and preliminary available data on case studies are presented. Index Terms: SOP testing, analog system testing, built-in testing, digital system testing, automatic test equipment, design for testability, manufacturing testing, self-testing, built-off testing.

This paper presents a compact, phase-locked loop (PLL) based, frequency synthesizer suitable for built-in testing and automatic tuning applications operating in the 100MHz frequency range. Key features of this design include a differential charge pump with common mode feedback (CMFB) and a voltage controlled oscillator (VCO) based on a pseudo-differential OTA with a linear transconductance control and tuning invariant output resistance. Experimental results from an integrated prototype fabricated using standard 0.35µm CMOS technology are presented. The measured HD3 of the output signal is better than-39dB over 80 % of the tuning range: 40-160MHz. The circuit occupies a silicon area of 200×1000µm 2 and operates from a 3.3V power supply. 2. FREQUENCY SYNTHESIZER The frequency synthesizer is based on a type-II PLL. It is formed by a phase-frequency detector (PFD), a differential charge pump with CMFB, an external differential third order loop filter, a quadrature VCO and a programmable frequency divider, as shown in Figure 1. f REF

I would like to express my sincerest gratitude to Prof. Abhijit Chatterjee for providing me the opportunity to work with him during my years at Georgia Tech. He has been a source of great inspiration and courage. His guidance has been invaluable for my research during these years. I also thank him for his advice and support on other aspects which have helped me immensely. I also take the opportunity to thank faculty members, Prof. Madhavan Swaminathan, Prof. David Anderson, Prof. Gregory Durgin, and Prof. Hao-Min Zhou for agreeing to serve on my committee and offering valuable suggestions and recommendations. I would also like to thank Semiconductor Research Corporation (SRC), Giga Scale