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Compilation for future nanocomputer architectures nanocomputer architectures
- International Conference on Computing in Nanotechnology, Las Vegas
, 2006
"... Compilation has a long history of translating a programmer’s human-readable code into machine instructions designed to make good use of a specific target computer. In this paper, we formalize a compiler framework that broadly defines the task of compilation to include output of a machine description ..."
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Cited by 5 (4 self)
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Compilation has a long history of translating a programmer’s human-readable code into machine instructions designed to make good use of a specific target computer. In this paper, we formalize a compiler framework that broadly defines the task of compilation to include output of a machine description customized to the input program which would be used to generate the target computer. The compiled program would then run on the generated computer. Inspired by research in design space exploration, this compilation approach exploits the proposed capabilities of nanocomputers, which are in the class of reconfigurable parallel architectures. This emerging hardware technology relies on molecular level fabricated circuit design to minimize feature size while creating a vast matrix of reconfigurable processing units, an application of the advancing field of nanotechnology. We identify design issues and present preliminary results that support earlier work in this area and propose future directions.
Processor frequency selection for SoC platforms for multimedia applications
- NUS, School of Computing
, 2004
"... Of late, there has been a considerable interest in generic and configurable System-on-Chip platforms specifically targeted towards implementing multimedia applications. A number of such platforms offer the possibility of including processor soft cores which are highly customizable. For voltage/frequ ..."
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Cited by 3 (2 self)
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Of late, there has been a considerable interest in generic and configurable System-on-Chip platforms specifically targeted towards implementing multimedia applications. A number of such platforms offer the possibility of including processor soft cores which are highly customizable. For voltage/frequency scaled processors, such customization includes the selection of appropriate voltage/frequency operating points which are tuned to the application set to be mapped onto the platform. In this context, we present an analytical framework that can guide a system designer in identifying the frequency ranges that should be supported by the different processors of a platform architecture. This framework can also be used to identify how such frequency ranges depend on the different parameters of the architecture (such as on-chip buffer sizes), and the performance impacts associated with selecting a particular frequency range. In the case of multimedia streaming applications, identifying such performance impacts and tradeoffs involved in customizing a platform architecture is especially difficult due to the bursty nature of on-chip traffic arising out of multimedia processing and the high variability in their execution requirements. The framework presented here is designed to precisely capture such characteristics and can be used in the design-space exploration of energy-aware platform architectures for multimedia processing. 1
Compiling a mechanical nanocomputer adder
- International Conference on Computer Design (CDES 2007), Las Vegas, electronic proceedings
, 2007
"... Abstract- Computer component fabrication is approaching physical limits of traditional photolithographic fabrication techniques. An alternative computer architecture may be enabled by the rapidly maturing field of nanotechnology, and consist of nanomechanical computational machines similar to those ..."
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Cited by 2 (2 self)
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Abstract- Computer component fabrication is approaching physical limits of traditional photolithographic fabrication techniques. An alternative computer architecture may be enabled by the rapidly maturing field of nanotechnology, and consist of nanomechanical computational machines similar to those first proposed by Eric Drexler, or other nanoscale components. In this study, we propose the design of a nanocompiler which targets a simulated hydrocarbon assembler. The compiler framework and resulting nano-mechanical machine is simulated using a component-level Colored Petri Net model of a 32-bit adder and an atomic-level gate simulator. Future work is proposed to extend the framework to simulate a full range nano-mechanical processing components.
Integrated Data Relocation and Bus Reconfiguration for Adaptive System-on-Chip Platforms
"... Abstract — Dynamic variations in application functionality and performance requirements can lead to the imposition of widely disparate requirements on System-on-Chip (SoC) platform hardware over time. This has led to interest in the design and use of adaptive SoC platforms that are capable of provid ..."
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Cited by 1 (0 self)
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Abstract — Dynamic variations in application functionality and performance requirements can lead to the imposition of widely disparate requirements on System-on-Chip (SoC) platform hardware over time. This has led to interest in the design and use of adaptive SoC platforms that are capable of providing high performance in the face of such variations. Recent advances in circuits and architectures are enabling platforms that contain various mechanisms for runtime adaptation. However, the problem of exploiting such configurability in a coordinated manner at the system level remains a challenging task. In this work, we focus on two configurable subsystems of SoC platforms that play a crucial role in determining overall system performance, namely, the on-chip communication architecture, and the on-chip memory architecture. Using detailed case studies, we demonstrate the limitations of designs in which the architectural configuration of a busbased communication architecture and the placement of data in memory are statically optimized, and those in which each is customized separately, without considering their interdependence. We propose an integrated methodology for dynamically relocating on-chip data and reconfiguring the communication architecture, and discuss the necessary hardware support. Experiments conducted on an SoC platform that integrates decoders for the UMTS (3G) and IEEE 802.11a (Wireless LAN) standards demonstrate that the proposed integrated adaptation technique helps boost the maximum achievable performance by up to 32 % over the best statically optimized design. I.
Configurable Platforms with Dynamic Platform Management: An Efficient Alternative to Application-Specific System-on-Chips
"... Emerging trends in system design indicate that in the future, a large role will be played by System-on-Chip (SoC) platforms consisting of general-purpose, configurable components. Commercially available SoC platforms provide some degrees of configurability, most of which are limited to one-time (sta ..."
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Cited by 1 (0 self)
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Emerging trends in system design indicate that in the future, a large role will be played by System-on-Chip (SoC) platforms consisting of general-purpose, configurable components. Commercially available SoC platforms provide some degrees of configurability, most of which are limited to one-time (static) customization of platform hardware. However, with increasing application diversity, time-varying requirements, and the convergence of multiple applications on the same platform, there is a growing need for SoC platforms that can be dynamically configured in order to adapt to changing requirements.
Abstract- The Cell Matrix Architecture is a massive array
"... of dynamically self-configurable, uniformly connected, identical computational units. This architecture can enable efficient, practical and powerful evolvable computing on the scale of quadrillions of logic gates. Nanotechnology manufacturing techniques likely will be necessary to produce a device a ..."
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of dynamically self-configurable, uniformly connected, identical computational units. This architecture can enable efficient, practical and powerful evolvable computing on the scale of quadrillions of logic gates. Nanotechnology manufacturing techniques likely will be necessary to produce a device at this scale in the future, with current Cell Matrix research focused on simulation at the circuit layout and switch level. This paper reports on a technique for Nanocompilation, the automatic compilation for such molecular-scale architectures, of high level programming language instructions into a functional Cell Matrix configuration. The focus of this work is on control structures, such as loops and decision statements, memory systems and arithmetic units, which are necessary components of any computer program. The framework of this compiler approach is presented, along with examples of generated circuits, a discussion of design issues, and results of an experimental evaluation.
Abstract
"... Current practice in scheduling on-chip resources for multimedia processing relies on techniques like stalling a processor when a buffer overflows and dynamically monitoring and adjusting processor shares available to the different multimedia streams. Furthermore, the parameters involved in designing ..."
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Current practice in scheduling on-chip resources for multimedia processing relies on techniques like stalling a processor when a buffer overflows and dynamically monitoring and adjusting processor shares available to the different multimedia streams. Furthermore, the parameters involved in designing a scheduler are determined using purely simulation-based techniques. Such techniques often lead to complicated scheduling algorithms, and are in general ad-hoc in nature without any worst-case performance guarantees. We present an analytical framework to systematically design and evaluate schedulers for such SoC multimedia processing platforms, and thereby help to address these problems. We show the utility of this framework through a detailed case study involving the design of a scheduler for a set-top box device. Categories and Subject Descriptions C.1.4 [Processor Architectures]: Parallel Architectures- Real-time distributed, Scheduling and task partitioning C.3.d [Special-Purpose and Application-Based Systems]: Real-time and embedded systems J.9.c [Mobile Applications]: Multimedia applications and multimedia signal processing
THE DEMAND FOR configurable SoC platforms that
"... Scheduling on-chip resources using analytical techniques is becoming increasingly important in multimedia processing. This article presents an analytical framework for designing and evaluating schedulers for SoC multimedia platforms. The modeling technique subsumes standard event models used in real ..."
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Scheduling on-chip resources using analytical techniques is becoming increasingly important in multimedia processing. This article presents an analytical framework for designing and evaluating schedulers for SoC multimedia platforms. The modeling technique subsumes standard event models used in real-time scheduling and accurately captures the variability in task execution requirements.
Dynamic Tuning of Configurable Architectures: The AWW Online Algorithm
"... ABSTRACT Architectures with software-writable parameters, or configurable architectures, enable runtime reconfiguration of computing platforms to the applications they execute. Such dynamic tuning can improve application performance, as well as energy. However, reconfiguring incurs a temporary perf ..."
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ABSTRACT Architectures with software-writable parameters, or configurable architectures, enable runtime reconfiguration of computing platforms to the applications they execute. Such dynamic tuning can improve application performance, as well as energy. However, reconfiguring incurs a temporary performance cost. Thus, online algorithms are needed that decide when to reconfigure and which configuration to choose such that overall performance is optimized. We introduce the adaptive weighted window (AWW) algorithm, and compare with several other algorithms, including algorithms previously developed by the online algorithm community. We describe experiments showing that AWW results are within 4% of the offline optimal on average. AWW outperforms the other algorithms, and is robust across three datasets and across three categories of application sequences too. AWW improves a non-dynamic approach on average by 6%, and by up to 30% in low-reconfiguration-time situations.
Compiling a Mechanical Nanocomputer Adder
"... Abstract- Computer component fabrication is approaching physical limits of traditional photolithographic fabrication techniques. An alternative computer architecture may be enabled by the rapidly maturing field of nanotechnology, and consist of nanomechanical computational machines similar to those ..."
Abstract
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Abstract- Computer component fabrication is approaching physical limits of traditional photolithographic fabrication techniques. An alternative computer architecture may be enabled by the rapidly maturing field of nanotechnology, and consist of nanomechanical computational machines similar to those first proposed by Eric Drexler, or other nanoscale components. In this study, we propose the design of a nanocompiler which targets a simulated hydrocarbon assembler. The compiler framework and resulting nano-mechanical machine is simulated using a component-level Colored Petri Net model of a 32-bit adder and an atomic-level gate simulator. Future work is proposed to extend the framework to simulate a full range nano-mechanical processing components.
