Abstract—A dual-path amplifier topology with dual-loop parallel compensation technique is proposed for low-power three-stage amplifiers. By using two parallel high-speed paths for high-frequency signal propagation, there is no passive capacitive feedback network loaded at the amplifier output. Both the bandwidth and slew rate are thus significantly improved. Implemented in a 0.6- m CMOS process, the proposed three-stage amplifier has over 100-dB gain, 7-MHz gain-bandwidth product, and 3.3-V / s average slew rate while only dissipating 330 W at 1.5 V, when driving a 25-k //120-pF load. The proposed amplifier achieves at least two times improvement in bandwidth-to-power and slew-rate-to-power efficiencies than all other reported multistage amplifiers using different compensation topologies. Index Terms—Amplifiers, dual loop, dual path, frequency compensation, multistage amplifiers. I.

Abstract—This paper presents a low-power stability strategy to significantly reduce the power consumption of a three-stage amplifier using active-feedback frequency compensation (AFFC). The bandwidth of the amplifier can also be enhanced. Simulation results verify that the power dissipation of the AFFC amplifier is reduced by 43 % and the bandwidth is improved by 32.5 % by using the proposed stability strategy. In addition, a dynamic feedforward stage (DFS), which can be embedded into the AFFC amplifier to improve the transient responses without consuming extra power, is proposed. Implemented in a 0.6- m CMOS process, experimental results show that both AFFC amplifiers with and without DFS achieve almost the same small-signal performances while the amplifier with DFS improves both the negative slew rate and negative 1 % settling time by two times. Index Terms—Active feedback, amplifiers, dynamic feedforward stage (DFS), frequency compensation, low-power stability strategy, multistage amplifiers. I.

Abstract—In this paper, the effect of load capacitance variation on the location of the closed loop poles of three-stage amplifiers is analyzed and a frequency compensation scheme that automatically adjusts the damping factor according to the load capacitance is proposed. A class-AB 16 headphone driver designed using the proposed scheme in 0.13 m technology can handle 1 pF to 22 nF capacitive load while consuming as low as 1.2 mW of quiescent power. It can deliver a peak power of 40 mW (1.6 Vpp swing) to the load with 84.8 dB THD and 92 dB peak SNR. It occupies 0.1 mm2 area. Index Terms—Class-AB amplifiers, class-AB drivers, audio power amplifiers, headphone drivers, multi-stage amplifiers, capacitive loaded amplifiers. Fig. 1. 16 driver configuration. I.