Abstract. A known method to compute on an asynchronously updating cellular automaton is the simulation of a synchronous computing model on it. Such a scheme requires not only an increased number of cell states, but also the simulation of a global synchronization mechanism. Asynchronous systems tend to use synchronization only on a local scale—if they use it at all. Research on cellular automata that are truly asynchronous has been limited mostly to trivial phenomena, leaving issues such as computation unexplored. This paper presents an asynchronously updating cellular automaton that conducts computation without relying on a simulated global synchronization mechanism. The 2-dimensional cellular automaton employs a Moore-neighborhood and 85 totalistic transition rules describing the asynchronous interactions between the cells. Despite the probabilistic nature of asynchronous updating, the outcome of the dynamics is deterministic. This is achieved by simulating delay insensitive circuits on it, a type of asynchronous circuit that is known for its robustness to variations in the timing of signals. We implement three primitive operators on the cellular automaton from which any arbitrary delay insensitive circuit can be constructed, and show how to connect the operators such that collisions of crossing signals are avoided.

Abstract — Delay-Insensitive (DI) circuits are a class of asynchronous circuits, whose correctness of operation is robust to arbitrary delays in modules or interconnection lines. Keller clarified the precise operating conditions of the class of DIcircuits, and presented a universal set of primitive modules from which any circuit in the class is realizable. Later, Patra presented an alternative universal set of primitive modules, and claimed that there is no universal set of primitives satisfying Keller’s conditions, in which the largest number of input and output lines of each primitive module is less than five. In this paper, we present new types of primitive modules, each having at most three input- and output-lines. and show they form a universal set of primitives. We achieve this reduction in complexity by allowing the input- and output-lines of modules to be bi-directional and to be able to buffer signals. The use of buffers in interconnection lines allows higher throughput of signals and results in circuits requiring less feedback lines, thus improving the efficiency of DI-circuits. The proposed class of DI-circuits is especially useful for implementations on cellular automata—an architecture that promises efficient implementations and manufacturing in nanotechnology due to its regular structure. Index Terms — asynchronous systems, delay-insensitive circuits, module, universality, bi-directional buffering lines I.

systematic approach