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Saturation: an efficient iteration strategy for symbolic state space generation
 PROC. TOOLS AND ALGORITHMS FOR THE CONSTRUCTION AND ANALYSIS OF SYSTEMS (TACAS), LNCS 2031
, 2001
"... We present a novel algorithm for generating state spaces of asynchronous systems using Multi–valued Decision Diagrams. In contrast to related work, we encode the next–state function of a system not as a single Boolean function, but as cross–products of integer functions. This permits the applicati ..."
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Cited by 56 (30 self)
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We present a novel algorithm for generating state spaces of asynchronous systems using Multi–valued Decision Diagrams. In contrast to related work, we encode the next–state function of a system not as a single Boolean function, but as cross–products of integer functions. This permits the application of various iteration strategies to build a system’s state space. In particular, we introduce a new elegant strategy, called saturation, and implement it in the tool SMART. On top of usually performing several orders of magnitude faster than existing BDD–based state–space generators, our algorithm’s required peak memory is often close to the final memory needed for storing the overall state space.
BottomUp Induction of Oblivious ReadOnce Decision Graphs
, 1994
"... . We investigate the use of oblivious, readonce decision graphs as structures for representing concepts over discrete domains, and present a bottomup, hillclimbing algorithm for inferring these structures from labelled instances. The algorithm is robust with respect to irrelevant attributes, and ..."
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Cited by 45 (8 self)
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. We investigate the use of oblivious, readonce decision graphs as structures for representing concepts over discrete domains, and present a bottomup, hillclimbing algorithm for inferring these structures from labelled instances. The algorithm is robust with respect to irrelevant attributes, and experimental results show that it performs well on problems considered difficult for symbolic induction methods, such as the Monk's problems and parity. 1 Introduction Top down induction of decision trees [25, 24, 20] has been one of the principal induction methods for symbolic, supervised learning. The tree structure, which is used for representing the hypothesized target concept, suffers from some wellknown problems, most notably the replication problem and the fragmentation problem [23]. The replication problem forces duplication of subtrees in disjunctive concepts, such as (A B) (C D); the fragmentation problem causes partitioning of the data into fragments, when a higharity attrib...
Saturation Unbound
 Proc. TACAS
, 2003
"... In previous work, we proposed a "saturation" algorithm for symbolic statespace generation characterized by the use of multivalued decision diagrams, boolean Kronecker operators, event locality, and a special iteration strategy. This approach outperforms traditional BDDbased techniques by several o ..."
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Cited by 41 (21 self)
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In previous work, we proposed a "saturation" algorithm for symbolic statespace generation characterized by the use of multivalued decision diagrams, boolean Kronecker operators, event locality, and a special iteration strategy. This approach outperforms traditional BDDbased techniques by several orders of magnitude in both space and time but, like them, assumes a priori knowledge of each submodel's state space. We introduce a new algorithm that merges explicit local statespace discovery with symbolic global statespace generation. This relieves the modeler from worrying about the behavior of submodels in isolation.
Verity  a Formal Verification Program for Custom CMOS Circuits
 IBM JOURNAL OF RESEARCH AND DEVELOPMENT
, 1994
"... In an effort to fully exploit CMOS performance, custom design techniques are used extensively in commercial microprocessor design. However, given the complexity of current generation processors and the necessity for manual designer intervention throughout the design process, proving design correc ..."
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Cited by 19 (5 self)
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In an effort to fully exploit CMOS performance, custom design techniques are used extensively in commercial microprocessor design. However, given the complexity of current generation processors and the necessity for manual designer intervention throughout the design process, proving design correctness is a major concern. In this paper we discuss Verity, a formal verification program for symbolically proving the equivalence between a highlevel design specification and a MOS transistorlevel implementation. Verity
Symbolic parametric safety analysis of linear hybrid systems with BDDlike datastructures
 IEEE TRANS. SOFTW. ENG
, 2004
"... We introduce a new BDDlike data structure called HybridRestriction Diagrams (HRDs) for the representation and manipulation of linear hybrid automata (LHA) statespaces and present algorithms for weakest precondition calculations. This permits us to reason about the valuations of parameters that ma ..."
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Cited by 18 (1 self)
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We introduce a new BDDlike data structure called HybridRestriction Diagrams (HRDs) for the representation and manipulation of linear hybrid automata (LHA) statespaces and present algorithms for weakest precondition calculations. This permits us to reason about the valuations of parameters that make safety properties satisfied. Advantages of our approach include the ability to represent discrete state information and concave polyhedra in a unified scheme, as well as to save both memory consumptions and manipulation times when processing the same substructures in statespace representations. Our experimental results document its efficiency in practice.
Exploiting Structural Similarities in a BDDbased Verification Method
 in Theorem Provers in Circuit Design. 1994, number 901 in Lecture Notes in Computer Science
, 1994
"... . A major challenge in the area of hardware verification is to devise methods that can handle circuits of practical size. This paper intends to show how the applicability of combinational circuit verification tools based on binary decision diagrams (BDDs) can be greatly improved. The introduction of ..."
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Cited by 13 (1 self)
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. A major challenge in the area of hardware verification is to devise methods that can handle circuits of practical size. This paper intends to show how the applicability of combinational circuit verification tools based on binary decision diagrams (BDDs) can be greatly improved. The introduction of dynamic variable ordering techniques already makes these tools more robust; a designer no longer needs to worry about a good initial variable order. In addition, we present a novel approach combining BDDs with a technique that exploits structural similarities of the circuits under comparison. We explain how these similarities can be detected and put to effective use in the verification process. Benchmark results show that the proposed method significantly extends the range of circuits that can be verified using BDDs. 1 Introduction The times when researchers in the CAD field could sit in their ivory tower thinking up neat solutions for theoretical problems belong to the past. Nowadays, ind...
Learning to Order BDD Variables in Verification
 Journal of Artificial Intelligence Research
, 2003
"... The size and complexity of software and hardware systems have significantly increased in the past years. As a result, it is harder to guarantee their correct behavior. One of the most successful methods for automated verification of finitestate systems is model checking. Most of the current mode ..."
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Cited by 12 (0 self)
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The size and complexity of software and hardware systems have significantly increased in the past years. As a result, it is harder to guarantee their correct behavior. One of the most successful methods for automated verification of finitestate systems is model checking. Most of the current modelchecking systems use binary decision diagrams (BDDs) for the representation of the tested model and in the verification process of its properties.
Exploiting interleaving semantics in symbolic statespace generation
 Formal Methods in System Design
"... Abstract. Symbolic techniques based on Binary Decision Diagrams (BDDs) are widely employed for reasoning about temporal properties of hardware circuits and synchronous controllers. However, they often perform poorly when dealing with the huge state spaces underlying systems based on interleaving sem ..."
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Cited by 8 (3 self)
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Abstract. Symbolic techniques based on Binary Decision Diagrams (BDDs) are widely employed for reasoning about temporal properties of hardware circuits and synchronous controllers. However, they often perform poorly when dealing with the huge state spaces underlying systems based on interleaving semantics, such as communications protocols and distributed software, which are composed of independently acting subsystems that communicate via shared events. This article shows that the efficiency of state–space exploration techniques using decision diagrams can be drastically improved by exploiting the interleaving semantics underlying many event–based and component–based system models. A new algorithm for symbolically generating state spaces is presented that (i) encodes a model’s state vectors with Multi–valued Decision Diagrams (MDDs) rather than flattening them into BDDs and (ii) partitions the model’s Kronecker–consistent next–state function by event and subsystem, thus enabling multiple lightweight next–state transformations rather than a single heavyweight one. Together, this paves the way for a novel iteration order, called saturation, which replaces the breadth–first search order of traditional algorithms. The resulting saturation algorithm is implemented in the tool SMART, and experimental studies show that it is often several orders of magnitude better in terms of time efficiency, final memory consumption, and peak memory consumption than existing symbolic algorithms.
Heuristics for BDD handling of sumofproducts formulae
 Proceedings of the European Safety and Reliability Association Conference, ESREL'98
, 1998
"... : This paper presents the result of research on heuristic methods for assessment of faulttrees (boolean formulae) using Binary Decision Diagrams (BDDs for short). BDDs are the stateoftheart compact representation of boolean formulae. The fault trees under consideration are given in the sumofpr ..."
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Cited by 6 (4 self)
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: This paper presents the result of research on heuristic methods for assessment of faulttrees (boolean formulae) using Binary Decision Diagrams (BDDs for short). BDDs are the stateoftheart compact representation of boolean formulae. The fault trees under consideration are given in the sumofproducts or productsofsums form. We propose a new heuristic that is both robust and discriminating on these particular formulae. The sizes of the BDD obtained are much smaller than those obtained using standard heuristics. However from the theoretical point of view the size of the corresponding BDD remains exponentially large in the worst case. Nevertheless, in practice we manage to deal with complex formulae by means of a new rewriting method which we propose in this article. 1 INTRODUCTION Faced with the intractability of most of the interesting properties of boolean formulae  assessing a fault tree, finding satisfying solutions, counting the number of solutionsit becomes necessary...
Free MDDBased Software Optimization Techniques for Embedded Systems
 In Proc. of the Conf. on Design Automation & Test in Europe
, 2000
"... Embedded systems make a heavy use of software to perform RealTime embeddedcontrol tasks. Embedded software is characterized by a relatively long lifetime and by tight cost, performance and safety constraints. Several superoptimization techniques for embedded softwares based on MultivaluedDecision ..."
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Cited by 5 (0 self)
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Embedded systems make a heavy use of software to perform RealTime embeddedcontrol tasks. Embedded software is characterized by a relatively long lifetime and by tight cost, performance and safety constraints. Several superoptimization techniques for embedded softwares based on MultivaluedDecision Diagram (MDD) representations have been described in the literature, but they all share the same basic limitation. They arebased on standardOrderedMDD (OMDD) packages, and hencerequireafixedorder of evaluation for the MDD variables on every execution path. Free MDDs (FMDDs) lift this limitation, and henceopen up more optimization opportunities. Finding the optimal variable ordering for FMDDs is a very difficult problem. Henceinthis paper we describe a heuristic procedure that performs well in practice, and is based on FMDD cost estimation applied to recursive cofactoring. Experimental results show that our new variable ordering method obtains often smaller embedded softwarethanprevious (siftingbased) methods.