Results 1  10
of
26
Saturation: an efficient iteration strategy for symbolic state space generation
 PROC. TOOLS AND ALGORITHMS FOR THE CONSTRUCTION AND ANALYSIS OF SYSTEMS (TACAS), LNCS 2031
, 2001
"... We present a novel algorithm for generating state spaces of asynchronous systems using Multi–valued Decision Diagrams. In contrast to related work, we encode the next–state function of a system not as a single Boolean function, but as cross–products of integer functions. This permits the applicati ..."
Abstract

Cited by 56 (30 self)
 Add to MetaCart
We present a novel algorithm for generating state spaces of asynchronous systems using Multi–valued Decision Diagrams. In contrast to related work, we encode the next–state function of a system not as a single Boolean function, but as cross–products of integer functions. This permits the application of various iteration strategies to build a system’s state space. In particular, we introduce a new elegant strategy, called saturation, and implement it in the tool SMART. On top of usually performing several orders of magnitude faster than existing BDD–based state–space generators, our algorithm’s required peak memory is often close to the final memory needed for storing the overall state space.
A performance study of BDDbased model checking
 IN PROCEEDINGS OF THE FORMAL METHODS ON COMPUTERAIDED DESIGN
, 1998
"... We present a study of the computational aspects of model checking based on binary decision diagrams (BDDs). By using a tracebased evaluation framework, we are able to generate realistic benchmarks and perform this evaluation collaboratively across several different BDD packages. This collaboration ..."
Abstract

Cited by 40 (4 self)
 Add to MetaCart
We present a study of the computational aspects of model checking based on binary decision diagrams (BDDs). By using a tracebased evaluation framework, we are able to generate realistic benchmarks and perform this evaluation collaboratively across several different BDD packages. This collaboration has resulted in significant performance improvements and in the discovery of several interesting characteristics of model checking computations. One of the main conclusions of this work is that the BDD computations in model checking and in building BDDs for the outputs of combinational circuits have fundamentally different performance characteristics. The systematic evaluation has also uncovered several open issues that suggest new research directions. We hope that the evaluation methodology used in this study will help lay the foundation for future evaluation of BDDbased algorithms.
Implementation of an efficient parallel BDD package
 In DAC
, 1996
"... Large BDD applications push computing resources to their limits. One solution to overcoming resource limitations is to distribute the BDD data structure across multiple networked workstations. This paper presents an efficient parallel BDD package for a distributed environment such as a network of wo ..."
Abstract

Cited by 39 (0 self)
 Add to MetaCart
Large BDD applications push computing resources to their limits. One solution to overcoming resource limitations is to distribute the BDD data structure across multiple networked workstations. This paper presents an efficient parallel BDD package for a distributed environment such as a network of workstations (NOW) or a distributed memory parallel computer. The implementation exploits a number of different forms of parallelism that can be found in depthfirst algorithms. Significant effort is made to limit the communication overhead, including a twolevel distributed hash table and an uncomputed cache. The package simultaneously executes multiple threads of computation on a distributed BDD. 1.
Efficient ExternalMemory Data Structures and Applications
, 1996
"... In this thesis we study the Input/Output (I/O) complexity of largescale problems arising e.g. in the areas of database systems, geographic information systems, VLSI design systems and computer graphics, and design I/Oefficient algorithms for them. A general theme in our work is to design I/Oeffic ..."
Abstract

Cited by 38 (12 self)
 Add to MetaCart
In this thesis we study the Input/Output (I/O) complexity of largescale problems arising e.g. in the areas of database systems, geographic information systems, VLSI design systems and computer graphics, and design I/Oefficient algorithms for them. A general theme in our work is to design I/Oefficient algorithms through the design of I/Oefficient data structures. One of our philosophies is to try to isolate all the I/O specific parts of an algorithm in the data structures, that is, to try to design I/O algorithms from internal memory algorithms by exchanging the data structures used in internal memory with their external memory counterparts. The results in the thesis include a technique for transforming an internal memory tree data structure into an external data structure which can be used in a batched dynamic setting, that is, a setting where we for example do not require that the result of a search operation is returned immediately. Using this technique we develop batched dynamic external versions of the (onedimensional) rangetree and the segmenttree and we develop an external priority queue. Following our general philosophy we show how these structures can be used in standard internal memory sorting algorithms
Synthesis of Wiring SignatureInvariant Equivalence Class Circuit Mutants and Applications to Benchmarking
, 1998
"... This paper formalizes the synthesis process of wiring signatur einvariant (WSI) combinational circuit mutants. The signature 0 is defined by a reference circuit 0, which itself is modeled as a canonic alform of a directed bipartite graph. A wiring perturbation induces a perturbed reference circuit ..."
Abstract

Cited by 28 (16 self)
 Add to MetaCart
This paper formalizes the synthesis process of wiring signatur einvariant (WSI) combinational circuit mutants. The signature 0 is defined by a reference circuit 0, which itself is modeled as a canonic alform of a directed bipartite graph. A wiring perturbation induces a perturbed reference circuit. A number of mutant circuits i can be resynthesized from the perturbed circuit. The mutants of interest are the ones that belong to the wiringsignature invariant equivalenc e classN 0, i.e. the mutants i 2N 0. Cir cuit mutants i 2N 0have a number of useful properties. For any wiring perturbation, the size of the wiring signatureinvariant equivalence class is huge. Notably, circuits in this class are not random, although for un biased testing and benchmarking purp oses, mutant selections from this class are typically random. For each reference circuit, we synthesized eight equivalence subclasses of circuit mutants, based on 0 to 100 % perturbation. Each subclass contains 100 randomly chosen mutant circuits, each listed in a different random order. The 14,400 benchmarking experiments with 3200 mutants in 4 equivalence classes, covering 13 typical EDA algorithms, demonstrate that an unbiased random selection of such circuits can lead to statistically meaningful differentiation and improvements of existing and new algorithms.
The I/OComplexity of Ordered BinaryDecision Diagram Manipulation
 UNIVERSITY OF AARHUS
, 1995
"... Ordered BinaryDecision Diagrams (OBDD) are the stateoftheart data structure for boolean function manipulation and there exist several software packages for OBDD manipulation. OBDDs have been successfully used to solve problems in e.g. digitalsystems design, verification and testing, in math ..."
Abstract

Cited by 28 (17 self)
 Add to MetaCart
Ordered BinaryDecision Diagrams (OBDD) are the stateoftheart data structure for boolean function manipulation and there exist several software packages for OBDD manipulation. OBDDs have been successfully used to solve problems in e.g. digitalsystems design, verification and testing, in mathematical logic, concurrent system design and in artificial intelligence. The OBDDs used in many of these applications quickly get larger than the avaliable main memory and it becomes essential to consider the problem of minimizing the Input/Output (I/O) communication. In this paper we analyze why existing OBDD manipulation algorithms perform poorly in an I/O environment and develop new I/Oefficient algorithms.
Binary Decision Diagrams on Network of Workstations
 Proc. of International Conference on Computer Design (ICCD'96
, 1996
"... The success of all binary decision diagram (BDD) based synthesis and verification algorithms depend on the ability to efficiently manipulate very large BDDs. We present algorithms for manipulation of very large Binary Decision Diagrams (BDDs) on a network of workstations (NOW). ANOW provides a colle ..."
Abstract

Cited by 22 (0 self)
 Add to MetaCart
The success of all binary decision diagram (BDD) based synthesis and verification algorithms depend on the ability to efficiently manipulate very large BDDs. We present algorithms for manipulation of very large Binary Decision Diagrams (BDDs) on a network of workstations (NOW). ANOW provides a collection of main memories and disks which can be used effectively to create and manipulate very large BDDs. To make efficient use of memory resources of a NOW, while completing execution in a reasonable amount of wall clock time, extension of breadthfirst technique is used to manipulate BDDs. BDDs are partitioned such that nodes for a set of consecutive variables are assigned to the same workstation. We present experimental results to demonstrate the capability of such an approach and point towards the potential impact for manipulating very large BDDs. 1 Introduction The manipulation of boolean functions is one of the most important operations in several areas of computeraided design such a...
Binary Decision Diagrams
 Calculational System Design, volume 173 of NATO Science Series F: Computer and Systems Sciences
, 1999
"... We review Binary Decision Diagrams presenting the properties and algorithms that are most relevant to their application to the verification of sequential systems. ..."
Abstract

Cited by 22 (0 self)
 Add to MetaCart
We review Binary Decision Diagrams presenting the properties and algorithms that are most relevant to their application to the verification of sequential systems.
High Performance BDD Package Based on Exploiting Memory Hierarchy
, 1996
"... The success of binary decision diagram (BDD) based algorithms for synthesis and/or verification depend on the availability of a high performance package to manipulate very large BDDs. Stateofthe art BDD packages, based on the conventional depthfirst technique, limit the size of the BDDs due to a ..."
Abstract

Cited by 20 (3 self)
 Add to MetaCart
The success of binary decision diagram (BDD) based algorithms for synthesis and/or verification depend on the availability of a high performance package to manipulate very large BDDs. Stateofthe art BDD packages, based on the conventional depthfirst technique, limit the size of the BDDs due to a disorderly memory access patterns that results in unacceptably high elapsed time when the BDD size exceeds the main memory capacity. We present a high performance BDD package that enables manipulation of very large BDDs by using an iterative breadthfirst technique directed towards localizing the memory accesses to exploit the memory system hierarchy. The new memoryoriented performance features of this package are 1) an architecture independent customized memory management scheme, 2) the ability to issue multiple independent BDD operations (superscalarity), and 3) the ability to perform multiple BDD operations even when the operands of some BDD operations are the result of some other operat...
Design of Experiments in BDD Variable Ordering: Lessons Learned
, 1998
"... Applying the Design of Experiments methodology to the evaluation of BDD variable ordering algorithms has yielded a number of conclusive results. The methodology relies on the recently introduced equivalence classes of functionally perturbed circuits that maintain logic invariance, or are within f1, ..."
Abstract

Cited by 16 (7 self)
 Add to MetaCart
Applying the Design of Experiments methodology to the evaluation of BDD variable ordering algorithms has yielded a number of conclusive results. The methodology relies on the recently introduced equivalence classes of functionally perturbed circuits that maintain logic invariance, or are within f1, 2, ...gminterms of the original reference circuit function, also maintaining entropyinvariance. For some of the current variable ordering algorithms and tools, the negative results include: (1) statistically significant sensitivity to naming of variables, (2) confirmation that a number of variable ordering algorithms are statistically equivalent to a random variable order assignment, and (3) observation of a statistically anomalous variable ordering behavior of a wellknown benchmark circuit isomorphic class when analyzed under a single and multiple outputs. On the positive side, the methodology supports a statistically significant merit evaluation of any newly introduced variable ordering ...