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Structuring and Automating Hardware Proofs in a HigherOrder TheoremProving Environment
 Formal Methods in System Design
, 1993
"... . In this article we present a structured approach to formal hardware verification by modelling circuits at the registertransfer level using a restricted form of higherorder logic. This restricted form of higherorder logic is sufficient for obtaining succinct descriptions of hierarchically design ..."
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Cited by 21 (7 self)
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. In this article we present a structured approach to formal hardware verification by modelling circuits at the registertransfer level using a restricted form of higherorder logic. This restricted form of higherorder logic is sufficient for obtaining succinct descriptions of hierarchically designed registertransfer circuits. By exploiting the structure of the underlying hardware proofs and limiting the form of descriptions used, we have attained nearly complete automation in proving the equivalences of the specifications and implementations. A hardwarespecific tool called MEPHISTO converts the original goal into a set of simpler subgoals, which are then automatically solved by a generalpurpose, firstorder prover called FAUST. Furthermore, the complete verification framework is being integrated within a commercial VLSI CAD framework. Keywords: hardware verification, higherorder logic 1 Introduction The past decade has witnessed the spiralling of interest within the academic com...
Formal Synthesis in Circuit Design  A Classification and Survey
, 1996
"... . This article gives a survey on different methods of formal synthesis. We define what we mean by the term formal synthesis and delimit it from the other formal methods that can also be used to guarantee the correctness of an implementation. A possible classification scheme for formal synthesis m ..."
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Cited by 12 (2 self)
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. This article gives a survey on different methods of formal synthesis. We define what we mean by the term formal synthesis and delimit it from the other formal methods that can also be used to guarantee the correctness of an implementation. A possible classification scheme for formal synthesis methods is then introduced, based on which some significant research activities are classified and summarized. We also briefly introduce our own approach towards the formal synthesis of hardware. Finally, we compare these approaches from different points of view. 1 Introduction In everyday use, synthesis means putting together of parts or elements so as to make up a complex whole. However in the circuit design domain, synthesis stands for a stepwise refinement of circuit descriptions from higher levels of abstraction (specifications) to lower ones (implementations), including optimizations within one abstraction level. Synthesis can be performed by hand for small circuits. Nowadays mor...
Modeling a Hardware Synthesis Methodology in Isabelle
 In Theorem Proving in Higher Order Logics (TPHOLs'96), volume 1125 of LNCS
, 1996
"... . Formal Synthesis is a methodology developed at Kent for combining circuit design and verification, where a circuit is constructed from a proof that it meets a given formal specification. We have reinterpreted this methodology in Isabelle's theory of higherorder logic so that circuits are inc ..."
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Cited by 6 (4 self)
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. Formal Synthesis is a methodology developed at Kent for combining circuit design and verification, where a circuit is constructed from a proof that it meets a given formal specification. We have reinterpreted this methodology in Isabelle's theory of higherorder logic so that circuits are incrementally built during proofs using higherorder resolution. Our interpretation simplifies and extends Formal Synthesis both conceptually and in implementation. It also supports integration of this development style with other proofbased synthesis methodologies and leads to techniques for developing new classes of circuits, e.g., recursive descriptions of parametric designs. Keywords: Hardware verification and synthesis, theorem proving, higherorder logic, higherorder unification. 1. Introduction Verification by formal proof is time intensive and this is a burden in bringing formal methods into software and hardware design. One approach to reducing the verification burden is to combine develop...
Verification of loop transformations for real time signal processing applications
 in VLSI Signal Processing VII
, 1994
"... ..."
A Logical Formalization of Hardware Design Diagrams
, 1994
"... Diagrams have been left as an informal tool in hardware reasoning, thus rendering them unacceptable representations within formal reasoning systems. We demonstrate some advantages of formally supporting diagrams in hardware verification systems via a simple example and provide a logical formalizatio ..."
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Cited by 4 (3 self)
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Diagrams have been left as an informal tool in hardware reasoning, thus rendering them unacceptable representations within formal reasoning systems. We demonstrate some advantages of formally supporting diagrams in hardware verification systems via a simple example and provide a logical formalization of hardware diagrams upon which we are constructing a verification tool. 1 Introduction The increased use of formal methods for verifying hardware specifications has generated a wealth of research into the formal models and representations of hardware that best facilitate the verification task. Most such models are based on combinations of temporal and higherorder logic which, while effective, do not necessarily reflect the models used during the design process. The hardware design process involves the use of a collection of diagrammatic forms, such as circuit diagrams and timing diagrams, which depict certain characteristics of hardware components more naturally than purely sentential r...
On the Effectiveness of Theorem Proving Guided Discovery of Formal Assertions for a Register Allocator in a HighLevel Synthesis System
 Proceedings of 11th Conference on Theorem Proving in Higher Or der Logics (TPHOL'98
"... . This paper presents a formal specification and a proof of correctness for the register optimization task in highlevel synthesis. A widely implemented register optimization algorithm is modeled in higherorder logic and verified in a theorem prover environment. A rich collection of correctness ..."
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Cited by 3 (3 self)
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. This paper presents a formal specification and a proof of correctness for the register optimization task in highlevel synthesis. A widely implemented register optimization algorithm is modeled in higherorder logic and verified in a theorem prover environment. A rich collection of correctness properties is systematically formulated during the theorem proving exercise. These properties constitute a detailed set of formal assertions that are identified with the invariants at various stages of the algorithm. The formal assertions are then embedded as programming assertions in the implementation of the register optimization algorithm in a productionstrength highlevel synthesis system. When turned on, the programming assertions (1) certify whether a specific run of the highlevel synthesis system produced designs with errorfree register allocation and, (2) in the event of a failure, help discover and isolate programming errors in the implementation. We present a detaile...
First Steps Towards Automating Hardware Proofs in HOL (Extended Abstract)
, 1991
"... ) Ramayya Kumar, Thomas Kropf, Klaus Schneider University of Karlsruhe, Institute of Computer Design and Fault Tolerance (Prof. Dr. ##. Schmid) P.O. Box 6980, W7500 Karlsruhe, Germany 1. INTRODUCTION The use of higherorder logic and an associated interactive theorem proving environment for hardwar ..."
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Cited by 2 (2 self)
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) Ramayya Kumar, Thomas Kropf, Klaus Schneider University of Karlsruhe, Institute of Computer Design and Fault Tolerance (Prof. Dr. ##. Schmid) P.O. Box 6980, W7500 Karlsruhe, Germany 1. INTRODUCTION The use of higherorder logic and an associated interactive theorem proving environment for hardware verification has established itself as an important technique for formal hardware validation [CaGM 86, FFFH 89]. In spite of the fact that such techniques are powerful and can be used for validation of complex systems, they continue to remain purely within the purview of theorem proving specialists. The only way to bring such a system closer to circuit designers is to augment the degree of automation and provide a camouflaged environment which mirrors the designer's view of hardware. The first step in this direction is to automate the proofs of all firstorder and simple higherorder statements, within such systems, which has been achieved by the tool FAUST [KuKS 91, ScKK 91a]. Further aut...
System Level Verification of Video and Image Processing Specifications
 In the proc. of ISSS
, 1995
"... A formal verification method is presented to verify the loop ordering of a high level transformed description against its original specification. The verification is done in an automatic way and its complexity is independent on the sizes of the loops bounds. Any practical structure of loop nests can ..."
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Cited by 2 (2 self)
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A formal verification method is presented to verify the loop ordering of a high level transformed description against its original specification. The verification is done in an automatic way and its complexity is independent on the sizes of the loops bounds. Any practical structure of loop nests can be handled. The method is especially suited for applications in the area of speech, image and video processing, frontend telecom and numerical computing systems which exhibit many loops and complex multidimensional signals. The efficiency of the approach is demonstrated on several realistic examples. 1 Introduction Practice shows that more than half of the total design effort can be taken up by verification or simulation at present [1]. Application studies in the area of speech, image and video processing, frontend telecom and numerical computing systems indicate that many algorithms operate on multi dimensional signals and exhibit a large amount of related control flow, especially exp...
Formally Correct Construction of Pipelined Processors
, 1998
"... A method of formally correct synthesis is presented, and applied to the automatic construction of pipelined processors. The method is based on a repertoire of elementary correctnesspreserving transformations which are efficiently crosschecked by an independent formal verification tool. Basic pipel ..."
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Cited by 2 (2 self)
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A method of formally correct synthesis is presented, and applied to the automatic construction of pipelined processors. The method is based on a repertoire of elementary correctnesspreserving transformations which are efficiently crosschecked by an independent formal verification tool. Basic pipelining strategies as well as automatic postsynthesis verification are provided. 1