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48
Axioms for memory access in asynchronous hardware systems
 ACM Transactions on Programming Languages and Systems
, 1986
"... The problem of concurrent accesses to registers by asynchronous components is considered. A set of axioms about the values in a register during concurrent accesses is proposed. It is shown that if these axioms are met by a register, then concurrent accesses to it may be viewed as nonconcurrent, thus ..."
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Cited by 81 (0 self)
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The problem of concurrent accesses to registers by asynchronous components is considered. A set of axioms about the values in a register during concurrent accesses is proposed. It is shown that if these axioms are met by a register, then concurrent accesses to it may be viewed as nonconcurrent, thus making it possible to analyze asynchronous algorithms without elaborate timing analysis of operations. These axioms are shown, in a certain sense, to be the weakest. Motivation for this work came from analyzing lowlevel hardware components in a VLSI chip which concurrently accesses a flipflop.
Universal Computation and Other Capabilities of Hybrid and Continuous Dynamical Systems
, 1995
"... We explore the simulation and computational capabilities of hybrid and continuous dynamical systems. The continuous dynamical systems considered are ordinary differential equations (ODEs). For hybrid systems we concentrate on models that combine ODEs and discrete dynamics (e.g., finite automata). We ..."
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Cited by 80 (3 self)
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We explore the simulation and computational capabilities of hybrid and continuous dynamical systems. The continuous dynamical systems considered are ordinary differential equations (ODEs). For hybrid systems we concentrate on models that combine ODEs and discrete dynamics (e.g., finite automata). We review and compare four such models from the literature. Notions of simulation of a discrete dynamical system by a continuous one are developed. We show that hybrid systems whose equations can describe a precise binary timing pulse (exact clock) can simulate arbitrary reversible discrete dynamical systems defined on closed subsets of R n . The simulations require continuous ODEs in R 2n with the exact clock as input. All four hybrid systems models studied here can implement exact clocks. We also prove that any discrete dynamical system in Z n can be simulated by continuous ODEs in R 2n+1 . We use this to show that smooth ODEs in R 3 can simulate arbitrary Turing machines, and henc...
Design and Implementation of a True Random Number Generator Based on
 Cryptographic Hardware and Embedded Systems  CHES 2003, Lecture Notes in Computer Science
, 2003
"... Abstract. There are many applications for true, unpredictable random numbers. For example the strength of numerous cryptographic operations is often dependent on a source of truly random numbers. Sources of random information are available in nature but are often hard to access in integrated circuit ..."
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Cited by 21 (0 self)
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Abstract. There are many applications for true, unpredictable random numbers. For example the strength of numerous cryptographic operations is often dependent on a source of truly random numbers. Sources of random information are available in nature but are often hard to access in integrated circuits. In some specialized applications, analog noise sources are used in digital circuits at great cost in silicon area and power consumption. These analog circuits are often influenced by periodic signal sources that are in close proximity to the random number generator. We present a random number generator comprised entirely of digital circuits, which utilizes electronic noise. Unlike earlier work [11], only standard digital gates without regard to precise layout were used. 1
An Asynchronous Communication Mechanism Using SelfTimed Circuits
 Proc. Async2000, Eilat
, 1999
"... A modified 4slot asynchronous communication mechanism (ACM) using entirely selftimed circuits to implement the algorithm is presented here. Mutual exclusion elements are used to concentrate potential metastability to a couple of discrete points so that it can be resolved entirely within the mechani ..."
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Cited by 13 (11 self)
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A modified 4slot asynchronous communication mechanism (ACM) using entirely selftimed circuits to implement the algorithm is presented here. Mutual exclusion elements are used to concentrate potential metastability to a couple of discrete points so that it can be resolved entirely within the mechanism itself, while the selftimed circuits allow the interface between the reader and writer processes and the mechanism to be minimised. Initial analyses show that this solution is more robust with regard to steering logic metastability, and can potentially run faster, than the original 4slot solution. 2 Introduction writer data in shared memory control variables reader Figure 1 Asynchronous data communication mechanisms using shared memory and control variables. Data communication between concurrent processes often employ shared memory which may have access conflicts when the processes are not synchronised. The most obvious way to protect shared memory is to put it into a critical section ...
PetriNet Based Investigation of SynchronisationFree Interprocess Communication in SharedMemory RealTime Systems
, 1997
"... This paper presents the results of the analysis of the synchronisationfree interprocesscommunications mechanisms using Petrinet based methods [3]. This provides an automated and more straightforward alternative verification of the validity of the previous analyses by Simpson, offers an easier fou ..."
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Cited by 10 (9 self)
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This paper presents the results of the analysis of the synchronisationfree interprocesscommunications mechanisms using Petrinet based methods [3]. This provides an automated and more straightforward alternative verification of the validity of the previous analyses by Simpson, offers an easier foundation for the investigation of the more general cases, and extensions to investigate the effects of metastability on the mechanism. This paper is intended to be read in conjunction with [1] and [2] which provide more detailed background information on the mechanisms including discussion of their practical and theoretical significance. 2 Modelling of the mechanisms
Ternary Simulation: A Refinement of Binary Functions or an Abstraction of RealTime Behaviour?
 PROCEEDINGS OF THE 3RD WORKSHOP ON DESIGNING CORRECT CIRCUITS (DCC96
, 1996
"... We prove the equivalence between the ternary circuit model and a notion of intuitionistic stabilization bounds. The results are obtained as an application of the timing interpretation of intuitionistic propositional logic presented in [12]. We show that if one takes an intensional view of the ternar ..."
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Cited by 10 (3 self)
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We prove the equivalence between the ternary circuit model and a notion of intuitionistic stabilization bounds. The results are obtained as an application of the timing interpretation of intuitionistic propositional logic presented in [12]. We show that if one takes an intensional view of the ternary model then the delays that have been abstracted away can be completely recovered. Our intensional soundness and completeness theorems imply that the extracted delays are both correct and exact; thus we have developed a framework which unifies ternary simulation and functional timing analysis. Our focus is on the combinational behaviour of gatelevel circuits with feedback.
Computing Synchronizer Failure Probabilities
, 2007
"... SystemonChip designs often have a large number of timing domains. Communication between these domains requires synchronization, and the failure probabilities of these synchronizers must be characterized accurately to ensure the robustness of the complete system. We present a novel approach for d ..."
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Cited by 10 (2 self)
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SystemonChip designs often have a large number of timing domains. Communication between these domains requires synchronization, and the failure probabilities of these synchronizers must be characterized accurately to ensure the robustness of the complete system. We present a novel approach for determining the failure probabilities of synchronizer circuits. We use numerical intergration to perform largesignal analysis that accounts for the nonlinear behaviour of real synchronizer circuits. We complement this with smallsignal techniques to characterize behaviours near the metastable equilibrium. This combination overcomes the limitations of traditional techniques: the largesignal analysis accounts for the transfer of metastable behaviour between synchronizer stages; and the smallsignal techniques overcome the limitations of numerical accuracy inherent in pure simulation approaches. Our approach is fully automated, is suitable for integration into circuit simulation tools such as SPICE, and enables accurate characterization of extremely small failure probabilities.
Timing Analysis of Combinational Circuits in Intuitionistic Propositional Logic
 Formal Methods in System Design
, 1999
"... Classical logic has so far been the logic of choice in formal hardware verification. This paper proposes the application of intuitionistic logic to the timing analysis of digital circuits. The intuitionistic setting serves two purposes. The modeltheoretic properties are exploited to handle the s ..."
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Cited by 7 (1 self)
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Classical logic has so far been the logic of choice in formal hardware verification. This paper proposes the application of intuitionistic logic to the timing analysis of digital circuits. The intuitionistic setting serves two purposes. The modeltheoretic properties are exploited to handle the secondorder nature of bounded delays in a purely propositional setting without need to introduce explicit time and temporal operators. The proof theoretic properties are exploited to extract quantitative timing information and to reintroduce explicit time in a convenient and systematic way. We present a natural Kripkestyle semantics for intuitionistic propositional logic, as a special case of a Kripke constraint model for Propositional Lax Logic [15], in which validity is validity up to stabilisation, and implication oe comes out as "boundedly gives rise to." We show that this semantics is equivalently characterised by a notion of realisability with stabilisation bounds as realisers...
Hardware Evolution: On the Nature of Artificially Evolved Electronic Circuits
 University of Sussex, UK
, 2001
"... of the work presented in this thesis has been previously published as listed below. Although some of these papers have coauthors, the work appearing in this thesis is entirely my own, with the exception of parts of chapter 3, which presents work jointly carried out by myself and Adrian Thompson. Th ..."
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Cited by 6 (1 self)
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of the work presented in this thesis has been previously published as listed below. Although some of these papers have coauthors, the work appearing in this thesis is entirely my own, with the exception of parts of chapter 3, which presents work jointly carried out by myself and Adrian Thompson. The respective contributions to this work will be explicitly stated at the beginning of the chapter. List of Previous Publications Kuntz, P., Layzell, P., & Snyers, D. (1997). A Colony of Antlike Agents for Partitioning
Faulttolerant Algorithms for TickGeneration in Asynchronous Logic: Robust Pulse Generation [Extended Abstract] ⋆
"... Abstract. The advances of deep submicron VLSI technology pose new challenges in designing robust systems, which can in principle be addressed by approaches established in faulttolerant distributed systems research. This paper is the first step in an attempt to develop a very robust highprecision c ..."
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Cited by 6 (4 self)
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Abstract. The advances of deep submicron VLSI technology pose new challenges in designing robust systems, which can in principle be addressed by approaches established in faulttolerant distributed systems research. This paper is the first step in an attempt to develop a very robust highprecision clocking system for hardware designs like systemsonchip for critical applications. It is devoted to the design and the correctness proof of a novel Byzantine faulttolerant selfstabilizing pulse synchronization protocol, which facilitates a direct implementation in standard asynchronous digital logic. Despite the severe implementation constraints, it offers optimal resilience and smaller complexity than all existing pulse synchronization protocols.