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Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program
 in Proc. of 16th International Conference on VLSI Design
, 2003
"... In the previous work, the problem of nding gate delays to eliminate glitches has been solved by linear programs (LP) requiring an exponentially large number of constraints. By introducing two additional variables per gate, namely, the fastest and the slowest arrival times, besides the gate delay,we ..."
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In the previous work, the problem of nding gate delays to eliminate glitches has been solved by linear programs (LP) requiring an exponentially large number of constraints. By introducing two additional variables per gate, namely, the fastest and the slowest arrival times, besides the gate delay,we reduce the number of the LP constraints to be linear in circuit size. For example, the 469gate c880 circuit requires 3,611 constraints as compared to the 6.95 million constraints needed with the previous method. The reduced constraints provably produce the same exact LP solution as obtained by the exponential set of constraints. For the rst time, we are able to optimize all ISCAS'85 benchmarks. For the c7552 circuit, when the input to output delay is constrained not to increase, a design with 366 delay bu ers consumes only 34 % peak and 38 % average power as compared to an unoptimized design. As shown in previous work, the use of delay bu ers is essential in this case. The practicality of the design is demonstrated by implementing an optimized 4bit ALU circuit for which the power consumption was obtained by a circuitlevel simulator. 1.
Variable Input Delay CMOS Logic for Low Power Design
 Auburn University
, 2005
"... Modern digital circuits consist of logic gates implemented in the complementary metal oxide semiconductor (CMOS) technology. The time taken for a logic gate output to change after one or more inputs have changed is called the delay of the gate. A conventional CMOS gate is designed to have the same i ..."
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Cited by 5 (0 self)
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Modern digital circuits consist of logic gates implemented in the complementary metal oxide semiconductor (CMOS) technology. The time taken for a logic gate output to change after one or more inputs have changed is called the delay of the gate. A conventional CMOS gate is designed to have the same input to output delay irrespective of which input caused the output to change. We propose a new gate design that has different delays along various input to output paths within the gate. This is accomplished by inserting selectively sized “permanently on ” series transistors at the inputs of the logic gate. We demonstrate the use of the variable input delay CMOS gates for a totally glitchfree minimum dynamic power implementation of a digital circuit. Applying a previously described linear programming method to the c7552 benchmark circuit, we obtained a power saving of 58 % over an unoptimized design. This power consumption was 18% lower than that for an alternative low power design using conventional CMOS gates. All circuits had the same overall delay. Since the overall delay was not allowed to increase, the glitch elimination with conventional gates required insertion of delay buffers on noncritical paths. The use of the variable input delay gates drastically reduced the required number of delay buffers. 1
Design of variable input delay gates for low dynamic power circuits
 PROC. THE INTERNATIONAL WORKSHOP ON POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION
, 2005
"... The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the output delay of the gate. A conventional multiinput CMOS gate is designed to have the same input to output delay irrespective of which input caused the output to change. A gate which can offe ..."
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Cited by 4 (0 self)
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The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the output delay of the gate. A conventional multiinput CMOS gate is designed to have the same input to output delay irrespective of which input caused the output to change. A gate which can offer different delays for different inputoutput paths through it, is known as a v ¯ ariable input delay(VID) gate and the maximum difference in delay between any two paths through the same gate is known as “ub”. These gates can be used for minimizing the active power of a digital CMOS circuit using a previosuly described technique called v ¯ ariable input delay(VID) logic. This previous publication proposed three different designs for implementating the VID gate. In this paper, we describe a technique for transistor sizing of these three flavors of the VID gate for a given delay requirement. We also describe techniques for calculating the ub of each flavor. We outline an algorithm for quick determination of the transistor sizes for a gate for a given load capacitance.
Printed in the United States of America Transistor Sizing of Logic Gates to Maximize Input Delay Variability
, 2005
"... The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the delay of the gate. A conventional multiinput CMOS gate is designed to have the same input to output delay irrespective of which input caused the output to change. A gate which can offer differe ..."
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The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the delay of the gate. A conventional multiinput CMOS gate is designed to have the same input to output delay irrespective of which input caused the output to change. A gate which can offer different delays for different inputoutput paths through it, is known as a variable input delay (VID) gate and the maximum difference in delays of any two paths through the gate is known as “ub. ” The VID gates have a known application in minimizing the active power of a digital CMOS circuit. A previous publication has proposed three different designs for implementing VID gates. In this paper, we describe transistor sizing methods to implement the three types of VID gates for any specified delay requirement. We also describe techniques for calculating the ub for each type of gate design. We outline an algorithm for an efficient determination of the transistor sizes for a gate for given delays and output load capacitance. The algorithm is a twostep approach with a lookup table of sizes in the first stage and a sensitivity based steepest descent method for the second stage. We also give a brief introduction to the power saving potential by maximizing ub when used in conjunction with the previously published technique.
A Generalized Minimum Dynamic Power and HighSpeed Design Methods for . . .
, 2004
"... We formulate a linear program (LP) to simultaneously minimize the dynamic power and overall delay of a CMOS circuit. To eliminate all glitches either without or with minimal number of delay buffers, a CMOS gate is assumed to have adjustable input to output delays for each input. Since these delays a ..."
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We formulate a linear program (LP) to simultaneously minimize the dynamic power and overall delay of a CMOS circuit. To eliminate all glitches either without or with minimal number of delay buffers, a CMOS gate is assumed to have adjustable input to output delays for each input. Since these delays are not independent, a transistor sizing problem would require very complex nonlinear optimization. We solve the problem in three steps. First, CMOS gates are analyzed to determine the realizable maximum differential input delay, ub, for the device technology being used. Second, an LP assumes the gate input and output delays as independent variables and determines them for all gates. This LP satisfies (1) glitch elimination conditions and the realizability constraint (ub) for all gates, and (2) the specified overall delay for the circuit. The total number of constraints in our LP is a linear function of the circuit size. Third, all gates are designed with the delays determined by the LP. As a sample result, using ub =10 when we designed the c1355 benchmark circuit specifying a large overall delay, a zero buffer design was obtained. It consumed 33 % power and had three times the overall delay as compared to an unoptimized design. When the overall delay was constrained not to increase, the lowpower design required 64 delay bu ers and consumed 37% power.
A Technique to Reduce Glitch Power during Physical Design Stage for Low Power and Less IR Drop Vasantha Kumar B.V.P
"... A glitch compensation methodology is proposed in this paper which involves in reducing the undesired switching of combinational circuits in order to save dynamic power. The proposed methodology can be seamlessly integrated to existing physical design flow to reduce the glitch power which is one of t ..."
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A glitch compensation methodology is proposed in this paper which involves in reducing the undesired switching of combinational circuits in order to save dynamic power. The proposed methodology can be seamlessly integrated to existing physical design flow to reduce the glitch power which is one of the major contributing factors for both dynamic and IR drop. A glitch is an undesired transition that occurs before intended value in digital circuits. A glitch occurs in CMOS circuits when differential delay at the inputs of a gate is greater than inertial delay, which results into notable amount of power consumption. The glitch power is becoming more prominent in lower technology nodes. Introduction of buffers at the input of the Logic gate may reduce glitches, but it results into large area overhead and