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Optimal design of a CMOS opamp via geometric programming
 IEEE Transactions on ComputerAided Design
, 2001
"... We describe a new method for determining component values and transistor dimensions for CMOS operational ampli ers (opamps). We observe that a wide variety of design objectives and constraints have a special form, i.e., they are posynomial functions of the design variables. As a result the ampli er ..."
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Cited by 54 (10 self)
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We describe a new method for determining component values and transistor dimensions for CMOS operational ampli ers (opamps). We observe that a wide variety of design objectives and constraints have a special form, i.e., they are posynomial functions of the design variables. As a result the ampli er design problem can be expressed as a special form of optimization problem called geometric programming, for which very e cient global optimization methods have been developed. As a consequence we can e ciently determine globally optimal ampli er designs, or globally optimal tradeo s among competing performance measures such aspower, openloop gain, and bandwidth. Our method therefore yields completely automated synthesis of (globally) optimal CMOS ampli ers, directly from speci cations. In this paper we apply this method to a speci c, widely used operational ampli er architecture, showing in detail how to formulate the design problem as a geometric program. We compute globally optimal tradeo curves relating performance measures such as power dissipation, unitygain bandwidth, and openloop gain. We show how the method can be used to synthesize robust designs, i.e., designs guaranteed to meet the speci cations for a
Optimization of Custom MOS Circuits by Transistor Sizing
 IEEE INTERNATIONAL CONFERENCE ON COMPUTERAIDED DESIGN
, 1996
"... Optimization of a circuit by transistor sizing is often a slow, tedious and iterative manual process which relies on designer intuition. Circuit simulation is carried out in the inner loop of this tuning procedure. Automating the transistor sizing process is an important step towards being able to r ..."
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Cited by 11 (5 self)
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Optimization of a circuit by transistor sizing is often a slow, tedious and iterative manual process which relies on designer intuition. Circuit simulation is carried out in the inner loop of this tuning procedure. Automating the transistor sizing process is an important step towards being able to rapidly design highperformance, custom circuits. JiffyTune is a new circuit optimization tool that automates the tuning task. Delay, rise/fall time, area and power targets are accommodated. Each (weighted) target can be either a constraint or an objective function. Minimax optimization is supported. Transistors can be ratioed and similar structures grouped to ensure regular layouts. Bounds on transistor widths are supported. JiffyTune uses
Optimization techniques for highperformance digital circuits
 in Proc. IEEE Int. Conf. ComputerAided Design (ICCAD
, 1997
"... The relentless push for high performance in custom digital circuits has led to renewed emphasis on circuit optimization or tuning. The parameters of the optimization are typically transistor and interconnect sizes. The design metrics are not just delay, transition times, power and area, but also ..."
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Cited by 10 (2 self)
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The relentless push for high performance in custom digital circuits has led to renewed emphasis on circuit optimization or tuning. The parameters of the optimization are typically transistor and interconnect sizes. The design metrics are not just delay, transition times, power and area, but also signal integrity and manufacturability. This tutorial paper discusses some of the recently proposed methods of circuit optimization, with an emphasis on practical application and methodology impact. Circuit optimization techniques fall into three broad categories. The rst is dynamic tuning, based on timedomain simulation of the underlying circuit, typically combined with adjoint sensitivity computation. These methods are accurate but require the specication of input signals, and are best applied to small data
ow circuits and \crosssections " of larger circuits. Ecient sensitivity computation renders feasible the tuning of circuits with a few thousand transistors. Second, static tuners employ static timing analysis to evaluate the performance of the circuit. All paths through the logic are simultaneously tuned, and no input vectors are required. Large control macros are best tuned by these methods. However, in the context of deep submicron custom design, the inaccuracy of the delay models employed by these methods often limits their utility. Aggressive dynamic or static tuning can push a circuit into a precipitous corner of the manufacturing process space, which is a problem addressed by the third class of circuit optimization tools, statistical tuners. Statistical techniques are used to enhance manufacturability or maximize yield. In addition to surveying the above techniques, topics such as the use of stateoftheart nonlinear optimization methods and special considerations for interconnect sizing, clock tree optimization and noiseaware tuning will be brie
y considered. 1
Circuit Optimization via Adjoint Lagrangians
 IEEE INTERNATIONAL CONFERENCE ON COMPUTERAIDED DESIGN
, 1997
"... The circuit tuning problem is best approached by means of gradientbased nonlinear optimization algorithms. For large circuits, gradient computation can be the bottleneck in the optimization procedure. Traditionally, when the number of measurements is large relative to the number of tunable paramete ..."
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Cited by 8 (4 self)
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The circuit tuning problem is best approached by means of gradientbased nonlinear optimization algorithms. For large circuits, gradient computation can be the bottleneck in the optimization procedure. Traditionally, when the number of measurements is large relative to the number of tunable parameters, the direct method [2] is used to repeatedly solve the associated sensitivity circuit to obtain all the necessary gradients. Likewise, when the parameters outnumber the measurements, the adjoint method [1] is employed to solve the adjoint circuit repeatedly for each measurement to compute the sensitivities. In this paper, we propose the adjoint Lagrangian method, which computes all the gradients necessary for augmentedLagrangianbased optimization in a single adjoint analysis. After the nominal simulation of the circuit has been carried out, the gradients of the merit function are expressed as the gradients of a weighted sum of circuit measurements. The weights are dependent on the nominal solution and on optimizer quantities such as Lagrange multipliers. By suitably choosing the excitations of the adjoint circuit, the gradients of the merit function are computed via a single adjoint analysis, irrespective of the number of measurements and the number of parameters of the optimization. This procedure requires close integration between the nonlinear optimization software and the circuit simulation program. The adjoint
MIDAS  a functional simulator for mixed digital and analog sampled data systems
, 1995
"... Automatic Synthesis of CMOS Digital/Analog Converters by Robert McKinstry Robinson Neff Doctor of Philosophy in Engineering  Electrical Engineering and Computer Sciences University of California at Berkeley Professor Paul R. Gray, Chair Synthesis of analog functional blocks in integrated ci ..."
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Cited by 7 (1 self)
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Automatic Synthesis of CMOS Digital/Analog Converters by Robert McKinstry Robinson Neff Doctor of Philosophy in Engineering  Electrical Engineering and Computer Sciences University of California at Berkeley Professor Paul R. Gray, Chair Synthesis of analog functional blocks in integrated circuits offers promise for improved designer productivity. By developing module generators for commonly used analog circuit elements, a synthesis methodology may be matched to a particular application, with approaches and algorithms determined by the particular needs of target circuit type. An analog circuit designer should be able to input design specifications and underlying technology information, and a synthesis methodology should determine circuit parameter values and dimensions, creating the required mask layouts. Slow, tedious design and redesign methods should be replaced by one in which the computer finds minimum cost designs which meet performance requirements. This work implements synthesis methods for a widely used analog block, the digital/analog converter (DAC).
1 3 5 7
, 2005
"... 3B2v8:06a=w ðDec 5 2003Þ:51c XML:ver:5:0:1 INTEGRATION, the VLSI journal] (]]]])]]]–]]] ASLIC: a low power CMOS analog circuit design automation ..."
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3B2v8:06a=w ðDec 5 2003Þ:51c XML:ver:5:0:1 INTEGRATION, the VLSI journal] (]]]])]]]–]]] ASLIC: a low power CMOS analog circuit design automation
Henry Chang
 In Proc. IEEE Custom Integrated Circuits Conference
, 1992
"... We describe a topdown, constraintdriven design methodology for Analog Circuits. We delineate some of the tools that support it. Finally, we conclude with examples to better illustrate the methodology and its integration with the tool set. ..."
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We describe a topdown, constraintdriven design methodology for Analog Circuits. We delineate some of the tools that support it. Finally, we conclude with examples to better illustrate the methodology and its integration with the tool set.
1 Optimal Design of a CMOS OpAmp via Geometric Programming
"... ABSTRACT We describe a new method for determining component values and transistor dimensions for CMOS operational amplifiers (opamps). We observe that a wide variety of design objectives and constraints have a special form, i.e., theyareposynomial functions of the design variables. As a result the ..."
Abstract
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ABSTRACT We describe a new method for determining component values and transistor dimensions for CMOS operational amplifiers (opamps). We observe that a wide variety of design objectives and constraints have a special form, i.e., theyareposynomial functions of the design variables. As a result the amplifier design problem can be expressed as a special form of optimization problem called geometric programming, for which very efficient global optimization methods have been developed. As a consequence we can efficiently determine globally optimal amplifier designs, or globally optimal tradeoffs among competing performance measures such as power, openloop gain, and bandwidth. Our method therefore yields completely automated synthesis of (globally) optimal CMOS amplifiers, directly from specifications. In this paper we apply this method to a specific, widely used operational amplifier architecture, showing in detail how to formulate the design problem as a geometric program. We compute globally optimal tradeoff curves relating performance measures such as power dissipation, unitygain bandwidth, and openloop gain. We show how the method can be used to synthesize robust designs, i.e., designs guaranteed to meet the specifications for a variety of process conditions and parameters. 1.1
Automatic Synthesis of CMOS Operational Amplifiers: A Fuzzy Optimization Approach
"... In this paper, we present a method for optimizing and automating the components and transistor sizing for CMOS operational amplifiers (opamps). The optimization approaches used for the synthesis of analog circuits are found to be very much rigid in terms of capturing human intentions. In this work, ..."
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In this paper, we present a method for optimizing and automating the components and transistor sizing for CMOS operational amplifiers (opamps). The optimization approaches used for the synthesis of analog circuits are found to be very much rigid in terms of capturing human intentions. In this work, we have observed that with the use of fuzzy membership functions, human intentions for expressing wide variety of requirements, e.g., minimize power, maximize gain, etc., which are often conflicting in nature, can be captured effectively in order to formulate the objective function. For each of the performance specifications of a given topology, a membership function is assigned to measure the degree of fulfillment of the objectives and the constraints. A number of objectives are optimized simultaneously by assigning weights to each of them representing their relative importance, and then by clustering together to form the objective function that is solved by an optimization algorithm. We have considered the channel length modulation parameter (λ) for the computation of DC bias point and small signal parameters. The design results obtained from our optimization algorithm showed an excellent match with those obtained from SPICE simulation for a number of opamp topologies. 1.