We present the Instruction Set Description Language, ISDL, a machine description language used to describe target architectures to a retargetable compiler. A retargetable compiler is capable of compiling application code into machine code for different processors. The features and flexibility of ISDL enable the description of vastly different architectures such as an ASIP VLIW processor and a commercial DSP microprocessor. For instance, unlike other machine description languages, ISDL explicitly supports constraints which define valid operation groupings within an instruction, increasing the range of specifiable architectures. We have written a tool which, given an ISDL description of a processor, can automatically generate an assembler for it. Ongoing work includes the development of an automatic code-generator generator. ISDL: An Instruction Set Description Language for Retargetability 2 DSP Core Program ROM RAM ASIC or ASIP Peripherals Figure 1: A heterogeneous system-on-a-chip 1...

This paper shows how thorough object code optimization has simplified a compiler and made it easy to retarget. The code generator forgoes case analysis and emits naive code that is improved by a retargetable object code optimizer. With this technique, cross-compilers have been built for seven machines, some in as few as three person days. These cross-compilers emit code comparable to host-specific compilers. Categories and Subject Descriptors: D.3.4 [Programming Languages]: Processors--code genera-tion; compilers; optimization

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nML is a formalism targetted for describing arbitrary single-processor computer architectures. nML works at the instruction set level, i.e. it hides implementation issues of the actual machine. nML can be used as an input language for a wide range of tools that need formal machine descriptions. Based on attribute grammars, nML is flexible and reasonably easy to use. Contents 1 Introduction 2 1.1 Where are Machine Descriptions needed? : : : : : : : : : : : : : : : : : : : : : : : : 2 1.2 Different Kinds of Machine Descriptions : : : : : : : : : : : : : : : : : : : : : : : : : 2 1.2.1 GCC's .md format : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 2 1.2.2 The VHDL Hardware Definition Language : : : : : : : : : : : : : : : : : : : 3 1.3 General aims of nML : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 4 1.3.1 Abstraction Level : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 4 1.3.2 Sharing in Descriptions : : : : : : :...

This paper presents the material needed for exposing the reader to the advantages of using Prolog as a language for describing succinctly most of the algorithms needed in prototyping and implementing compilers or producing tools that facilitate this task. The available published material on the subject describes one particular approach in implementing compilers using Prolog. It consists of coupling actions to recursive descent parsers to produce syntax-trees which are subsequently utilized in guiding the generation of assembly language code. Although this remains a worthwhile approach, there is a host of possibilities for Prolog usage in compiler construction. The primary aim of this paper is to demonstrate the use of Prolog in parsing and compiling. A second, but equally important, goal of this paper is to show that Prolog is a labor-saving tool in prototyping and implementing many non-numerical algorithms which arise in compiling, and whose description using Prolog is not available in the literature. The paper discusses the use of unification and nondeterminism in compiler writing as well as means to bypass these (costly) features when they are deemed unnecessary. Topics covered include bottom-up and top-down parsers, syntax-directed translation, grammar properties, parser generation, code generation, and optimixations. Newly proposed features that are useful in compiler construction are also discussed. A knowledge of Prolog is assumed.

BURS theory provides a powerful mechanism to efficiently generate pattern matches in a given expression tree. BURS, which stands for bottom-up rewrite system, is based on term rewrite systems, to which costs are added. We formalise the underlying theory, and derive an algorithm that computes all pattern matches. This algorithm terminates if the term rewrite system is finite. We couple this algorithm with the well-known search algorithm A* that carries out pattern selection. The search algorithm is directed by a cost heuristic that estimates the minimum cost of code that has yet to be generated. The advantage of using a search algorithm is that we need to compute only those costs that may be part of an optimal rewrite sequence (and not the costs of all possible rewrite sequences as in dynamic programming). A system that implements the algorithms presented in this work has been built.

. We describe a novel technique for code selection based on data-flow graphs, which arise naturally in the domain of digital signal processing. Code selection is the optimized mapping of abstract operations to partial machine instructions. The presented method performs an important task within the retargetable microcode generator CBC, which was designed to cope with the requirements arising in the context of custom digital signal processor (DSP) programming. The algorithm exploits a graph representation in which control-flow is modeled by scopes. 1 Introduction In the domain of medium-throughput digital signal processing, micro-programmable processor cores are frequently chosen for system realization. By adding dedicated hardware (accelerator paths), these cores are tailored to the needs of new applications. Optimized processor modules can be reused, which is a major benefit compared to high-level synthesis [28] where a completely new design is developed for each application. ...

The design of an instruction set processor includes several related design tasks: instruction set design, microarchitecture design, and code generation. Although there have been automatic approaches for each individual task, the investigation of the interaction between these tasks still primarily relies on designers' experience and ingenuity. It is thus the goal of this research to develop formal models and algorithms to investigate such interaction systematically. This dissertation presents a two-phase co-synthesis approach to the problem. In the architectural level, given a set of application benchmarks and a pipeline structure, the ASIA (Automatic Synthesis of Instruction set Architecture) design automation system generates an instruction set and allocates hardware resources which best fit the applications, and, at the same time, maps the applications to assembly code with the synthesized instruction set. This approach formulates the codesign problem as a modified scheduling/allocat...

In an era of rapid design of microprocessors for desktop systems, embedded systems, and handheld computing devices, the timely construction of systems software is essential. Systems software, such as assemblers, compilers, and debuggers, must be constructed before development of application software for a microprocessor can commence. However, the implementation of such machine-specific applications is difficult and time consuming. Therefore, to remain competitive, it is imperative that systems software designs focus on portability to reduce implementation time and ensure rapid delivery of complete systems to the market. This dissertation presents the Computing System Description Language (CSDL) framework that addresses these rapid development requirements. We illustrate the CSDL framework by developing an instruction-set description component (RTL), an optional procedure calling convention description component (CCL), and the mechanism we use to extend extant descriptions (CSDL). RTL and its accompanying microinstruction descriptions (RTL) further the state-of-the-art in specifying semantics of machine instructions. RTL adds a new type system and abstract syntax that facilitates more accurate specification and automatic detection of errors by RTL manipulators. RTL machine descriptions are also application independent---they completely separate the specification of semantics from the application's implementation. The CCL specification language is the first work to formally describe procedure calling conventions. We demonstrate two distinct uses for CCL descriptions: code generation and fault detection. Using CCL we have built compilers that are more robust, and found and diagnosed faults in production compilers. CCL, RTL, and RTL descriptions are bound together u...

Instruction selection is a key component of code generation. High quality instruction selection is of particular importance in the embedded space where complex instruction sets are common and code size is a prime concern. Although instruction selection on tree expressions is a well understood and easily solved problem, instruction selection on directed acyclic graphs is NP-complete. In this paper we present NOLTIS, a near-optimal, linear time instruction selection algorithm for DAG expressions. NOLTIS is easy to implement, fast, and effective with a demonstrated average code size improvement of 5.1 % compared to the traditional tree decomposition and tiling approach.