Counterexample generation is a crucial task for error diagnosis and debugging of sequential circuits. The simpler a counterexample is – i.e. more general and fewer assigned input values – the better it can be understood by humans. We will use the concept of Black Boxes – parts of the design with unknown behavior – to mask out components for counterexample computation. By doing this, the resulting counterexample will argue about a reduced number of components in the system in order to facilitate the task of understanding and correcting the error effect. 1

Abstract—In this paper we present a procedure for solving quantified boolean formulas (QBF), which uses And-Inverter Graphs (AIGs) as the core data-structure. We make extensive use of structural information extracted from the input formula such as functional definitions of variables and non-linear quantifier structures. We show how this information can directly be exploited by the symbolic, AIG based representation. We implemented a prototype QBF solver based on our ideas and performed a number of experiments proving the effectiveness of our approach, and moreover, showing that our method is able to solve QBF instances on which state-of-the-art QBF solvers known from literature fail. I.

Abstract — Computing counterexamples is a crucial task for error diagnosis and debugging of sequential systems. If an implementation does not fulfill its specification, counterexamples are used to explain the error effect to the designer. In order to be understood by the designer, counterexamples should be simple, i.e. they should be as general as possible and assign values to a minimal number of input signals. Here we use the concept of Black Boxes — parts of the design with unknown behavior — to mask out components for counterexample computation. By doing so, the resulting counterexample will argue about a reduced number of components in the system to facilitate the task of understanding and correcting the error. We introduce the notion of ‘uniform counterexamples’ to provide an exact formalization of simplified counterexamples arguing only about components which were not masked out. Our computation of counterexamples is based on symbolic methods using AIGs (And-Inverter-Graphs). Experimental results using a VLIW processor as a case study clearly demonstrate our capability of providing simplified counterexamples. I.

This paper presents a light-weight sweeping method, similar to SAT- and BDD-sweeping. Performance are on the order of 10x to 100x faster than SAT-sweeping for large designs, while achieving about 50-90 % of the reductions. 1

This paper develops theoretical foundations and presents a practical algorithm for optimizing multi-output Boolean function M(x) whose outputs are combined using Boolean OR operator into a single-output Boolean function S(x). The proposed algorithm simplifies the logic structure of function M(x) and may change or remove some of its outputs, while preserving the functionality of function S(x). Applications of the proposed algorithm are (1) optimization of Boolean networks containing multi-input AND/OR gates, (2) minimization of sets of interpolants in interpolationbased model checking, (3) minimization of the structural representations of sets of states in circuit-based reachability analysis, to mention just a few. Experiments will be conducted to show the practicality of the proposed approach. 1.

Abstract—Reset is one of the most important signals in many designs. Since reset is typically not timing critical, it is handled at late physical design stages. However, the large fanout of reset and the lack of routing resources at these stages can create variant delays on different targets of the reset signal, creating reset recovery problems. Traditional approaches address this problem using physical design methods such as buffer insertion or rerouting. However, these methods may invalidate previous optimization efforts, making timing closure difficult. In this work we propose a formal method to calculate reset recovery slacks for registers at the register transfer level. Designers and physical design tools can then utilize this information throughout the design flow to reduce reset problems at later design stages. I.