Clock distribution networks are an important design issue that is highly dependent on delay variations and load imbalances, while requiring power efficiency. Existing mesh solutions significantly increase the dissipated power, whereas existing link based methods only address skew caused by variations and do not consider power consumption. The power dissipated by the inserted crosslinks within a buffered clock tree is investigated in this paper, and is shown to be a strong function of the resistance and capacitance of the crosslink. A crosslink may be power efficient despite the presence of short-circuit currents caused by multiple drivers in a non-tree clock network. The power characteristics of crosslink size and placement are also discussed, showing that the crosslink is best placed as close as possible to the target leaves of the tree. Crosslink insertion as both an alternative and complement to buffer sizing for low power skew reduction is also considered. Categories and Subject Descriptors B.7.m [Integrated Circuits]: Miscellaneous maintain balance. Non-tree topologies vary from a tree with a limited number of additional crosslinks [9]-[12] to a complete mesh structure [5]-[8], where a crosslink is a wire segment that connects two tree nodes and a mesh is a set of crosslinks that connects all or a significant group of adjacent nodes within a specific level of a clock tree (see Figure 1). Mesh structures are designed to balance each of the clock delays at the leaves or at some intermediate level of the tree [5]-[8]. These topologies, however, increase the total wire length, resulting in higher capacitance and, consequently, significantly increased dynamic power consumption. Thus, power is traded off for skew. General Terms: Design Keywords: Non-tree clock distribution network, clock tree,

Clock distribution in VLSI designs is of crucial importance and it is also a major source of power dissipation of a system. For today’s high performance microprocessors, clock signals are usually distributed by a global clock grid covering the whole chip, followed by post-grid routing that connects clock loads to the clock grid. Early study [7] shows that about 18.1 % of the total clock capacitance dissipation was due to this post-grid clock routing (i.e., lower mesh wires plus clock twig wires). This post-grid clock routing problem is thus an important one but not many previous works have addressed it. In this paper, we try to solve this problem of connecting clock ports to the clock grid through reserved tracks on multiple metal layers, with delay and slew constraints. Note that a set of routing tracks are reserved for this grid-to-ports clock wires in practice because of the conventional modular design style of high-performance microprocessors. We propose a new expansion algorithm based on the heap data structure to solve the problem effectively. Experimental results on industrial test cases show that our algorithm can improve over the latest work on this problem [10] significantly by reducing the capacitance by 24.6% and the wire length by 23.6%. We also validate our results using hspice simulation. Finally, our approach is very efficient and for larger test cases with about 2000 ports, the runtime is in seconds.

Influence of manufacturing variability on circuit performance has been increasing because of finer manufacturing process and lowered supply voltage. In this paper, we focus on mesh-style clock distribution which is believed to be effective for reducing clock skew, and we evaluate clock skew considering manufacturing and design variabilities. Considering MOS transistor variation- random and spatially-correlated variation- and non-uniform flip-flop (FF) placement, we demonstrate that spatially-correlated variation and severe non-uniform FF distribution can be major sources of clock skew. We also examine the dependency of clock skew on design parameters, and reveal that finer clock mesh does not necessarily reduce clock skew. 1.

This paper presents a self-compensation scheme of manufacturing variability for clock skew reduction. In the proposed scheme, a CDN with embedded variability sensors tunes variable clock drivers for canceling the clock skew induced by manufacturing variability. We apply the proposed scheme for a mesh-style CDN in a 65nm technology and evaluate the deskewing effect as a function of the sensor performance. Experimental results show that the skew can be reduced by over 70 % and the correlation coefficient between estimated and actual variabilities, which represents the sensor performance, should be more than 0.3 for skew reduction.

Abstract: Power is a primary concern in modern circuits. Clock distribution networks, in particular, are an essential element of a synchronous digital circuit and a significant power consumer. Clock distribution networks are subject to clock skew due to process, voltage, and temperature (PVT) variations and load imbalances. A target skew between sequentially-adjacent registers can be obtained in a balanced low power clock tree using techniques such as buffer and wire sizing. Existing skew mitigation techniques in tree-based clock distribution networks, however, are not efficient in coping with post design variations; whereas the latest non-tree mesh-based solutions reliably handle skew variations, albeit with a significant increase in dissipated power. Alternatively, crosslink-based methods provide low power and variation-efficient skew solutions. Existing crosslink-based methods, however, only address skew at the network topology level and do not target low power consumption. Different methods to manage skew and skew variations within tree and non-tree clock distribution networks are reviewed and compared in this paper. Guidelines for inserting crosslinks within a buffered low power clock tree are provided. Metrics to determine the most power efficient technique for a given circuit are discussed and verified with simulation. Keywords: low power; skew; skew variation; crosslinks; mesh; topologiesJ. Low Power Electron. Appl.2011, 1 220 1.

Abstract—Designing a high-quality clock network is very important in very large-scale integrated designs today, as it is the clock network that synchronizes all the elements of a chip, and it is also a major source of power dissipation of a system. Early study by Pham et al. in 2006 shows that about 18.1 % of the total clock capacitance was due to this postgrid clock routing (i.e., lower mesh wires plus clock twig wires). In this paper, we proposed a partition-based path expansion algorithm to solve this postgrid clock routing problem effectively. Experimental results on industrial test cases show that our algorithm can improve over the latest work by Shelar on this problem significantly by reducing the wire capacitance by 24.6 % and the wirelength by 23.6%. Index Terms—Clock routing, microprocessor design, postgrid. I.