Most of today's video and digital cameras use CCD image sensors, where the electric charge collected by the photodetector array during exposure time is serially shifted out of the sensor chip resulting in slow readout speed and high power consumption. Recently developed CMOS image sensors, by comparison, are read out non-destructively and in a manner similar to a digital memory and can thus be operated at very high frame rates. A CMOS image sensor can also be integrated with other camera functions on the same chip ultimately leading to a single-chip digital camera with very compact size, low power consumption and additional functionality. CMOS image sensors, however, generally su#er from lower dynamic range than CCDs due to their high read noise and non-uniformity. Moreover, as sensor design follows CMOS technology scaling, well capacity will continue to decrease, eventually resulting in unacceptably low SNR.

Abstract — We describe and analyze a novel CMOS pixel for high speed, low light imaging applications. The new pixel achieves lower dark current and noise and increased gain in comparison with conventional three-transistor, one-photodiode active pixel sensors without sacrificing speed and scalability to large arrays. It accomplishes this by biasing the photodiode of each pixel near zero volts and by separating the photodiode from the floating diffusion integration node. An image sensor with a 256 × 256 array of these pixels was designed for a commercially available 0.18 µm CMOS technology. The pixel size is 5µm × 5µm with a fill factor of 31%. The chip area is 3000µm × 3000µm. 1.8 V and 3.3 V power supplies are used for logic and sensor array, respectively. Differential output and chip level correlated-double sampling are used to suppress fixed pattern noise. Transmission gates with dummy transistors are incorporated into the readout chain to reduce both clock feedthrough and charge injection. I.

ACKNOWLEDGEMENTS I want to thank all the members of my group, my advisor, and my committee for all their help and time.

The role of CMOS Image Sensors since their birth around the 1960s, has been changing a lot. Unlike the past, current CMOS Image Sensors are becoming competitive with regard to Charged Couple Device (CCD) technology. They offer many advantages with respect to CCD, such as lower power consumption, lower voltage operation, on-chip functionality and lower cost. Nevertheless, they are still too noisy and less sensitive than CCDs. Noise and sensitivity are the key-factors to compete with industrial and scientific CCDs. It must be pointed out also that there are several kinds of CMOS Image sensors, each of them to satisfy the huge demand in different areas, such as Digital photography, industrial vision, medical and space applications, electrostatic sensing, automotive, instrumentation and 3D vision systems. In the wake of that, a lot of research has been carried out, focusing on problems to be solved such as sensitivity, noise, power consumption, voltage operation, speed imaging and dynamic range. In this paper, CMOS Image Sensors are reviewed, providing information on the latest advances achieved, their applications, the new challenges and their limitations. In conclusion, the State-of-the-art of CMOS Image Sensors.

Abstract — In this paper we present a CMOS image sensor design with a better sensitivity to low light intensity. This feature is achieved through a multi-resolution analog-todigital converter (ADC). By doing so, the photo-electrical characteristic of a sensor cell can is finely tuned. A costeffective architecture for realizing the required ADC is also proposed. This architecture leads to a faster conversion time as well as a smaller area. A simulation environment with postlayout accuracy is incorporated to demonstrate the advantages. It shows that a number of images can be captured more clearly than a traditional sensor 1. Index Terms — sensor, nonlinear ADC, logarithmic, photo diode. characteristic is not perfect. From a human’s perspective, an ideal pixel should have a logarithmic output response as shown in Fig. 2.