Abstract — With the continuous downscaling of CMOS technologies, the reliability has become a major bottleneck in the evolution of the next generation systems. Technology trends such as transistor down-sizing, use of new materials, and system on chip architectures continue to increase the sensitivity of systems to soft errors. These errors are random and not related to permanent hardware faults. Their causes may be internal (e.g., interconnect coupling) or external (e.g., cosmic radiation). To meet the system reliability requirements it is necessary for both the circuit designers and test engineers to get the basic knowledge of the soft errors. We present a tutorial study of the radiation-induced single event upset phenomenon caused by external radiation, which is a major source of soft errors. We summarize basic radiation mechanisms and the resulting soft errors in silicon. Soft error mitigation techniques with time and space redundancy are illustrated. An industrial design example, the IBM z990 system, shows how the industry is dealing with soft errors these days. I.

Nanometer CMOS VLSI circuits are highly sensitive to soft errors due to environmental causes such as cosmic radiation and charged particles. These phenomena, also known as single-event upset (SEU) induce current pulses at random times and random locations in a digital circuit. In this paper we model neutron-induced soft errors using two parameters, namely, frequency and intensity. Our soft error rate (SER) estimation method propagates both frequency (expressed as probability) and intensity as the width of single event transient (SET) pulses expressed as probability density functions through the circuit. With this model we are able to accurately model electrical masking factors in logic circuits. Also, the error pulse width density information at primary outputs of the logic circuit allows evaluation of SER reduction schemes such as time or space redundancy. 1

Abstract — While facing continuously shrinking feature sizes, the demand for fault tolerance in digital circuits increases. Numerous approaches to achieve robustness on the design side have been presented. But ensuring that the fault tolerance is really achieved is a tough verification problem. Here, we propose a formal model and an effective algorithm to formally prove the robustness of a digital circuit. The proposed model uses a fixed bound in time to cope with the complexity of the sequential equivalence check. The result is a lower and an upper bound on the robustness. The underlying algorithm and techniques to improve the efficiency are presented. In the experiments the method was evaluated on circuits with different fault detection mechanisms.

Abstract — One of the key challenges in nanoelectronics design is the decreasing reliability due to radiation induced single-event upsets. Without detailed device level simulations or physical experimentation, circuit level models can generate misleading reliability information. We present the results from a screening experiment to identify significant parameters in circuit level SEU simulations. We show that cell supply voltage, sizing parameters, and transient waveform descriptions have an important impact on design and should therefore be considered with care in circuit level designs. Larger variations in parameters can lead to soft error rate estimates that vary by more than 4 orders of magnitude, even small variations can lead to 15x variation in soft error rate estimation for a design. We present our methodology for screening and a ranking based on significance of several parameters involved in soft error simulation at the SPICE level. Index Terms — circuit level reliability, single event upset (SEU), soft-error rate (SER), Plackett and Burman design, Qcrit I.

Abstract — Due to continuous technology scaling, the reduction of nodal capacitances and the lowering of power supply voltages result in an ever decreasing minimal charge capable of upsetting the logic state of memory circuits. In this paper we investigate the critical charge (Q crit) required to upset a 6T SRAM cell designed in a commercial 90nm process. We characterize Q crit using different current models and show that there are significant differences in Q crit values depending on which models are used. Discrepancies in critical charge characterization are shown to result in under-predictions of the SRAM’s associated soft error rate as large as two orders of magnitude. For accurate Q crit calculation, it is critical that 3D device simulation is used to calibrate the current pulse modeling heavy ion strikes on the circuit, since the stimuli characteristics are technology feature size dependant. Current models with very fast characteristic timing parameters are shown to result in conservative soft error rate predictions; and can assertively be used to model ion strikes when 3D simulation data is not available. I.

Abstract—Technology roadmap projects nanoscale multibillion-transistor integration in the coming years. However, on-chip memory becomes increasingly exposed to the dual challenges of device-level reliability degradation and architecture-level performance gap. In this paper, we propose to exploit the inherent memory soft (transient) redundancy for on-chip memory design. Due to the mismatch between fixed cache line size and runtime variations in memory spatial locality, many irrelevant data are fetched into the memory thereby wasting memory spaces. The proposed soft-redundancy allocated memory detects and utilizes these memory spaces for jointly achieving efficient memory access and effective error control. A runtime reconfiguration scheme is also proposed to further enhance the soft-redundancy allocation. Simulation results demonstrate 74.8 % average error-control coverage ratio on the SPEC CPU2000 benchmarks with average of 59.5 % and 41.3 % reduction in memory miss rate and bandwidth usage, respectively, as compared to the existing memory techniques. Furthermore, the proposed technique is fully scalable with respect to various memory configurations. Index Terms—Cache memory, memory architecture, redundancy, reliability, error tolerance, access performance, bandwidth usage, VLSI design. I.

Due to current technology scaling trends such as shrinking feature sizes and reducing supply voltages, circuit reliability has become more susceptible to radiation-induced transient faults (soft errors). Soft errors, which have been a great concern in memories, are now a main factor in reliability degradation of logic circuits. In this paper, we propose a novel framework based on redundancy addition and removal (RAR) for soft error rate (SER) reduction. Several metrics and constraints are introduced to guide our proposed framework towards SER reduction in an efficient manner. Experimental results show that up to 70% reduction in output failure probability can be achieved with relatively low area overhead.

Soft errors in combinational and sequential elements of digital circuits are an increasing concern as a result of technology scaling. Several techniques for gate and latch hardening have been proposed to synthesize circuits that are tolerant to soft errors. However, each such technique has associated overheads of power, area, and performance. In this paper, we present a new methodology to compute the failures in time (FIT) rate of a sequential circuit where the failures are at the system-level. System-level failures are detected by monitors derived from functional specifications. Our approach includes efficient methods to compute the FIT rate of combinational circuits (CFIT), incorporating effects of logical, timing, and electrical masking. The contribution of circuit components to the FIT rate of the overall circuit can be computed from the CFIT and probabilities of system-level failure due to soft errors in those elements. Designers can use this information to perform Pareto-optimal hardening of selected sequential and combinational components against soft errors. We present experimental results demonstrating that our analysis is efficient, accurate, and provides data that can be used to synthesize a low-overhead, low-FIT sequential circuit. 1.

Steadily shrinking feature sizes of circuits are the guarantee to keep up with Moore’s law. But this also degrades the reliability of individual components continuously. Realizing correctly working circuits using unreliable components is a main objective for future design flows. In this work we present a technique to automatically synthesize robust circuits, i.e. circuits that are able to detect a transient fault. The BDD-based synthesis technique MuTaTe [1] is used to enable functional tests. Similar to the razor approach [2], these tests are performed in a time multiplexed scheme instead of adding redundant logic. As a result the area overhead in comparison to a non-robust circuit for the same function is often negligible. Experimental results for benchmark circuits are provided. Key words Synthesis, Robustness, Synthesis for Testability

Due to reduction in device feature size and supply voltage, the sensitivity to radiation induced transient faults of digital systems increases dramatically. In this paper, we present two approaches to evaluating the susceptibility of sequential circuits to soft errors. The first approach uses Markov chain theory, but can only provide steady-state behavior information. The second approach uses symbolic modeling based on BDDs/ADDs and circuit unrolling. The SER evaluation using this approach is demonstrated by the set of experimental results, which show that, for most of the benchmarks used, the SER decreases well below a given threshold (10-7 FIT) within ten clock cycles after the hit. The results obtained with the proposed symbolic framework are within 4 % average error and up to 11000X faster when compared to HSPICE detailed circuit simulation. The framework can be used for selective gate sizing targeting radiation hardening leading up to 80 % SER reduction when applied to a subset of ISCAS’89 benchmarks.