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24
Asymptotic Probability Extraction for NonNormal Distributions of Circuit Performance
 IEEE ICCAD
, 2004
"... While process variations are becoming more significant with each new IC technology generation, they are often modeled via linear regression models so that the resulting performance variations can be captured via Normal distributions. Nonlinear (e.g. quadratic) response surface models can be utilized ..."
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Cited by 46 (7 self)
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While process variations are becoming more significant with each new IC technology generation, they are often modeled via linear regression models so that the resulting performance variations can be captured via Normal distributions. Nonlinear (e.g. quadratic) response surface models can be utilized to capture larger scale process variations; however, such models result in nonNormal distributions for circuit performance which are difficult to capture since the distribution model is unknown. In this paper we propose an asymptotic probability extraction method, APEX, for estimating the unknown random distribution when using nonlinear response surface modeling. APEX first uses a novel binomial moment evaluation to efficiently compute the high order moments of the unknown distribution, and then applies moment matching to approximate the characteristic function of the random circuit performance by an efficient rational function. A simple statistical timing example and an analog circuit example demonstrate that APEX can provide better accuracy than Monte Carlo simulation with 10 4 samples and achieve orders of magnitude more efficiency. We also show the error incurred by the popular Normal modeling assumption using standard IC technologies. 1.
Asymptotic probability extraction for nonnormal performance distributions
 IEEE TRANS. CAD
, 2007
"... While process variations are becoming more significant with each new IC technology generation, they are often modeled via linear regression models so that the resulting performance variations can be captured via normal distributions. Nonlinear response surface models (e.g., quadratic polynomials) c ..."
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Cited by 18 (9 self)
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While process variations are becoming more significant with each new IC technology generation, they are often modeled via linear regression models so that the resulting performance variations can be captured via normal distributions. Nonlinear response surface models (e.g., quadratic polynomials) can be utilized to capture larger scale process variations; however, such models result in nonnormal distributions for circuit performance. These performance distributions are difficult to capture efficiently since the distribution model is unknown. In this paper, an asymptoticprobabilityextraction (APEX) method for estimating the unknown random distribution when using a nonlinear response surface modeling is proposed. The APEX begins by efficiently computing the highorder moments of the unknown distribution and then applies moment matching to approximate the characteristic function of the random distribution by an efficient rational function. It is proven that such a momentmatching approach is asymptotically convergent when applied to quadratic response surface models. In addition, a number of novel algorithms and methods, including binomial moment evaluation, PDF/CDF shifting, nonlinear companding and reverse evaluation, are proposed to improve the computation efficiency and/or approximation accuracy. Several circuit examples from both digital and analog applications demonstrate that APEX can provide better accuracy than a Monte Carlo simulation with 104 samples and achieve up to 10 × more efficiency. The error, incurred by the popular normal modeling assumption for several circuit examples designed in standard IC technologies, is also shown.
Performancecentering optimization for systemlevel analog design exploration
 Proc. of 2005 IEEE/ACM ComputerAided Design Conference (ICCAD2005
, 2005
"... In this paper we propose a novel analog design optimization methodology to address two key aspects of topdown systemlevel design: (1) how to optimally compare and select analog system architectures in the early phases of design; and (2) how to hierarchically propagate performance specifications fr ..."
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Cited by 8 (0 self)
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In this paper we propose a novel analog design optimization methodology to address two key aspects of topdown systemlevel design: (1) how to optimally compare and select analog system architectures in the early phases of design; and (2) how to hierarchically propagate performance specifications from system level to circuit level to enable independent circuit block design. Importantly, due to the inaccuracy of earlystage systemlevel models, and the increasing magnitude of process and environmental variations, the systemlevel exploration must leave sufficient design margin to ensure a successful latestage implementation. Therefore, instead of minimizing a design objective function, and thereby converging on a constraint boundary, we apply a novel performance centering optimization. Our proposed methodology centers the analog design in the performance space, and maximizes the distance to all constraint boundaries. We demonstrate that this earlystage design margin, which is measured by the volume of the inscribed ellipsoid lying inside the performance constraints, provides an excellent quality measure for comparing different system architectures. The efficacy of our performance centering approach is shown for analog design examples, including a complete clock data recovery system design and implementation. 1.
Templatefree symbolic performance modeling of analog circuits via canonicalform functions and genetic programming
 IEEE Trans. on CAD
, 2009
"... Abstract—This paper presents CAFFEINE, a method to automatically generate compact, interpretable symbolic performance models of analog circuits with no prior specification of an equation template. CAFFEINE uses SPICE simulation data, to model arbitrary nonlinear circuits and circuit characteristics ..."
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Cited by 5 (1 self)
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Abstract—This paper presents CAFFEINE, a method to automatically generate compact, interpretable symbolic performance models of analog circuits with no prior specification of an equation template. CAFFEINE uses SPICE simulation data, to model arbitrary nonlinear circuits and circuit characteristics. CAFFEINE expressions are canonical form functions: productofsum layers alternating with sumofproduct layers, as defined by a grammar. Multiobjective genetic programming trades off error with model complexity. On test problems, CAFFEINE models demonstrate lower prediction error than posynomials, splines, neural networks, kriging, and support vector machines. This paper also demonstrates techniques to scale CAFFEINE to larger problems.
Efficient Parametric Yield Estimation of Analog/Mixed Signal Circuits via Bayesian Model Fusion
"... Parametric yield estimation is one of the most criticalyetchallenging tasks for designing and verifying nanoscale analog and mixedsignal circuits. In this paper, we propose a novel Bayesian model fusion (BMF) technique for efficient parametric yield estimation. Our key idea is to borrow the simula ..."
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Cited by 5 (4 self)
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Parametric yield estimation is one of the most criticalyetchallenging tasks for designing and verifying nanoscale analog and mixedsignal circuits. In this paper, we propose a novel Bayesian model fusion (BMF) technique for efficient parametric yield estimation. Our key idea is to borrow the simulation data from an early stage (e.g., schematiclevel simulation) to efficiently estimate the performance distributions at a late stage (e.g., postlayout simulation). BMF statistically models the correlation between earlystage and latestage performance distributions by Bayesian inference. In addition, a convex optimization is formulated to solve the unknown latestage performance distributions both accurately and robustly. Several circuit examples designed in a commercial 32 nm CMOS process demonstrate that the proposed BMF technique achieves up to 3.75 × runtime speedup over the traditional kernel estimation method. 1.
Quadratic Statistical MAX Approximation for Parametric Yield Estimation of Analog/RF Integrated Circuits
"... Abstract—In this paper, we propose an efficient numerical algorithm for estimating the parametric yield of analog/RF circuits, considering largescale process variations. Unlike many traditional approaches that assume normal performance distributions, the proposed approach is particularly developed ..."
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Cited by 4 (2 self)
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Abstract—In this paper, we propose an efficient numerical algorithm for estimating the parametric yield of analog/RF circuits, considering largescale process variations. Unlike many traditional approaches that assume normal performance distributions, the proposed approach is particularly developed to handle multiple correlated nonnormal performance distributions, thereby providing better accuracy than the traditional techniques. Starting from a set of quadratic performance models, the proposed parametric yield estimation conceptually maps multiple correlated performance constraints to a single auxiliary constraint by using a MAX operator. As such, the parametric yield is uniquely determined by the probability distribution of the auxiliary constraint and, therefore, can easily be computed. In addition, two novel numerical algorithms are derived from moment matching and statistical Taylor expansion, respectively, to facilitate efficient quadratic statistical MAX approximation. We prove that these two algorithms are mathematically equivalent if the performance distributions are normal. Our numerical examples demonstrate that the proposed algorithm provides an error reduction of 6.5 times compared to a normaldistributionbased method while achieving a runtime speedup of 10–20 times over the Monte Carlo analysis with 103 samples. Index Terms—Analog/RF circuits, MAXoperator, parametric yield.
Regular Analog/RF Integrated Circuits Design Using Optimization With Recourse Including Ellipsoidal Uncertainty
, 2008
"... Abstract—Long design cycles due to the inability to predict silicon realities are a wellknown problem that plagues analog/RF integrated circuit product development. As this problem worsens for nanoscale IC technologies, the high cost of design and multiple manufacturing spins causes fewer products ..."
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Cited by 3 (0 self)
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Abstract—Long design cycles due to the inability to predict silicon realities are a wellknown problem that plagues analog/RF integrated circuit product development. As this problem worsens for nanoscale IC technologies, the high cost of design and multiple manufacturing spins causes fewer products to have the volume required to support fullcustom implementation. Design reuse and analog synthesis make analog/RF design more affordable; however, the increasing process variability and lack of modeling accuracy remain extremely challenging for nanoscale analog/RF design. We propose a regular analog/RF IC using metalmask configurability design methodology Optimization with Recourse of Analog Circuits including Layout Extraction (ORACLE), which is a combination of reuse and shareduse by formulating the synthesis problem as an optimization with recourse problem. Using a twostage geometric programming with recourse approach, ORACLE solves for both the globally optimal shared and applicationspecific variables. Furthermore, robust optimization is proposed to treat the design with variability problem, further enhancing the ORACLE methodology by providing yield bound for each configuration of regular designs. The statistical variations of the process parameters are captured by a confidence ellipsoid. We demonstrate ORACLE for regular Low Noise Amplifier designs using metalmask configurability, where a range of applications share common underlying structure and applicationspecific customization is performed using the metalmask layers. Two RF oscillator design examples are shown to achieve robust designs with guaranteed yield bound. Index Terms—Configurable design, optimization with recourse, robustness, statistical optimization. I.
Novel Algorithms for Fast Statistical Analysis of Scaled Circuits
, 2007
"... As VLSI technology moves to the nanometer scale for transistor feature sizes, the impact of manufacturing imperfections result in large variations in the circuit performance. Traditional CAD tools are not wellequipped to handle this scenario, since they do not model this statistical nature of the c ..."
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Cited by 2 (1 self)
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As VLSI technology moves to the nanometer scale for transistor feature sizes, the impact of manufacturing imperfections result in large variations in the circuit performance. Traditional CAD tools are not wellequipped to handle this scenario, since they do not model this statistical nature of the circuit parameters and performances, or if they do, the existing techniques tend to be oversimplified or intractably slow. We draw upon ideas for attacking parallel problems in other technical fields, such as computational finance, machine learning and hydrology, and synthesize them with innovative attacks for our problem domain of integrated circuits, to develop novel solutions to problems of efficient statistical analysis of circuits in the nanometer regime. In particular, this thesis makes three contributions: 1) SiLVR, a nonlinear response surface modeling (RSM) and performancedriven dimensionality reduction strategy, that uses the concepts of projection pursuit and latent variable regression to obtain an absolute improvement in modeling error of up to 34% over the best quadratic RSM method. SiLVR also captures the designer’s insight into the circuit behavior, by automatically extracting quantitative measures of relative
Bayesian Model Fusion: LargeScale Performance Modeling of Analog and MixedSignal Circuits by Reusing EarlyStage Data
"... Efficient highdimensional performance modeling of today’s complex analog and mixedsignal (AMS) circuits with largescale process variations is an important yet challenging task. In this paper, we propose a novel performance modeling algorithm that is referred to as Bayesian Model Fusion (BMF). Our ..."
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Efficient highdimensional performance modeling of today’s complex analog and mixedsignal (AMS) circuits with largescale process variations is an important yet challenging task. In this paper, we propose a novel performance modeling algorithm that is referred to as Bayesian Model Fusion (BMF). Our key idea is to borrow the simulation data generated from an early stage (e.g., schematic level) to facilitate efficient highdimensional performance modeling at a late stage (e.g., post layout) with low computational cost. Such a goal is achieved by statistically modeling the performance correlation between early and late stages through Bayesian inference. Several circuit examples designed in a commercial 32nm CMOS process demonstrate that BMF achieves up to 9 × runtime speedup over the traditional modeling technique without surrendering any accuracy. 1.
Globally Reliable VariationAware Sizing of Analog Integrated Circuits via Response Surfaces and Structural Homotopy
"... Abstract—This paper presents SANGRIA, a tool for automated globally reliable variationaware sizing of analog integrated circuits. Its keys to efficient search are adaptive response surface modeling, and a new concept, structural homotopy. Structural homotopy embeds homotopystyle objective functio ..."
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Abstract—This paper presents SANGRIA, a tool for automated globally reliable variationaware sizing of analog integrated circuits. Its keys to efficient search are adaptive response surface modeling, and a new concept, structural homotopy. Structural homotopy embeds homotopystyle objective function tightening into the search state’s structure, not dynamics. Searches at several different levels are conducted simultaneously: The loosest level does nominal dc simulation, and tighter levels add more analyses and {process, environmental} corners. New randomly generated designs are continually fed into the lowest (cheapest) level, always trying new regions to avoid premature convergence. For further efficiency, SANGRIA adaptively constructs response surface models, from which new candidate designs are optimally chosen according to both yield optimality on model and model prediction uncertainty. The stochastic gradient boosting models support arbitrary nonlinearities, and have linear scaling with input dimension and sample size. SANGRIA uses SPICE in the loop, supports accurate/complex statistical SPICE models, and does not make assumptions about the convexity or differentiability of the objective function. SANGRIA is demonstrated on four different analog circuits having from 10 to 50 devices and up to 444 design/process/environmental variables. Index Terms—Analog, design automation, integrated circuit, process variation. I.