In the previous work, the problem of nding gate delays to eliminate glitches has been solved by linear programs (LP) requiring an exponentially large number of constraints. By introducing two additional variables per gate, namely, the fastest and the slowest arrival times, besides the gate delay,we reduce the number of the LP constraints to be linear in circuit size. For example, the 469-gate c880 circuit requires 3,611 constraints as compared to the 6.95 million constraints needed with the previous method. The reduced constraints provably produce the same exact LP solution as obtained by the exponential set of constraints. For the rst time, we are able to optimize all ISCAS'85 benchmarks. For the c7552 circuit, when the input to output delay is constrained not to increase, a design with 366 delay bu ers consumes only 34 % peak and 38 % average power as compared to an unoptimized design. As shown in previous work, the use of delay bu ers is essential in this case. The practicality of the design is demonstrated by implementing an optimized 4-bit ALU circuit for which the power consumption was obtained by a circuit-level simulator. 1.

Abstract{A new low-power design method produces CMOS circuits that consume the least dynamic power at the highest speed permitted under the technology constraint. A gate is characterized by an inertial delay and separate delays between its inputs and output. The technology constraint, related tofeasible ranges of lengths and widths of transistors, is speci ed bya parameter u b.Itistheupper bound on the di erence between the input to output delays corresponding to any pair of inputs of a gate. We formulate a linear program (LP) whose size is proportional to the circuit size. This LP determines the inertial delay as well as input to output delays for each gate of the circuit with the given u b, such that all glitches are eliminated and the overall delay of the circuit is minimized. Because of the additional exibility in specifying gate delays, the glitch suppression is guaranteed without any delay bu ers. Hence this design consumes less power than those designed by other methods. We designed the circuit c1355 with 46 % of the original power dissipation compared toareference design. A previously published method, that characterizes each gate with a single delay, produced a c1355 circuit consuming 58% of the original power. Both low-power circuits had the same overall delay. The previous design required 224 delay bu ers, whereas the new design needed none. 1.

The power dissipated in a CMOS circuit consists of dynamic power, leakage power and short-circuit power components. The topic of this paper is the reduction of dynamic power. When an input vector is applied to the primary inputs (PI), the minimum power requirement for each gate output is to produce

There are many ways of combining the transistors to perform the logic functions such as NOT, NAND and NOR. We will describe the CMOS design style which is the most prominent in current day technologies.