Results 1 
5 of
5
Design of variable input delay gates for low dynamic power circuits
 PROC. THE INTERNATIONAL WORKSHOP ON POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION
, 2005
"... The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the output delay of the gate. A conventional multiinput CMOS gate is designed to have the same input to output delay irrespective of which input caused the output to change. A gate which can offe ..."
Abstract

Cited by 4 (0 self)
 Add to MetaCart
The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the output delay of the gate. A conventional multiinput CMOS gate is designed to have the same input to output delay irrespective of which input caused the output to change. A gate which can offer different delays for different inputoutput paths through it, is known as a v ¯ ariable input delay(VID) gate and the maximum difference in delay between any two paths through the same gate is known as “ub”. These gates can be used for minimizing the active power of a digital CMOS circuit using a previosuly described technique called v ¯ ariable input delay(VID) logic. This previous publication proposed three different designs for implementating the VID gate. In this paper, we describe a technique for transistor sizing of these three flavors of the VID gate for a given delay requirement. We also describe techniques for calculating the ub of each flavor. We outline an algorithm for quick determination of the transistor sizes for a gate for a given load capacitance.
Variable Input Delay CMOS Logic for Low Power Design
 Auburn University
, 2005
"... Modern digital circuits consist of logic gates implemented in the complementary metal oxide semiconductor (CMOS) technology. The time taken for a logic gate output to change after one or more inputs have changed is called the delay of the gate. A conventional CMOS gate is designed to have the same i ..."
Abstract

Cited by 4 (0 self)
 Add to MetaCart
Modern digital circuits consist of logic gates implemented in the complementary metal oxide semiconductor (CMOS) technology. The time taken for a logic gate output to change after one or more inputs have changed is called the delay of the gate. A conventional CMOS gate is designed to have the same input to output delay irrespective of which input caused the output to change. We propose a new gate design that has different delays along various input to output paths within the gate. This is accomplished by inserting selectively sized “permanently on ” series transistors at the inputs of the logic gate. We demonstrate the use of the variable input delay CMOS gates for a totally glitchfree minimum dynamic power implementation of a digital circuit. Applying a previously described linear programming method to the c7552 benchmark circuit, we obtained a power saving of 58 % over an unoptimized design. This power consumption was 18% lower than that for an alternative low power design using conventional CMOS gates. All circuits had the same overall delay. Since the overall delay was not allowed to increase, the glitch elimination with conventional gates required insertion of delay buffers on noncritical paths. The use of the variable input delay gates drastically reduced the required number of delay buffers. 1
Variable Input Delay CMOS Logic Design for Low Dynamic Power Circuits
 in Proc. 15th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS’05
, 2005
"... A gate that offers different delays for different inputoutput paths through it, is known as a variable input delay (VID) gate. The upper bound on this differential delay capability is specified by the parameter “ub”. These gates can be used to minimize the active power of a digital CMOS circuit by ..."
Abstract

Cited by 2 (1 self)
 Add to MetaCart
A gate that offers different delays for different inputoutput paths through it, is known as a variable input delay (VID) gate. The upper bound on this differential delay capability is specified by the parameter “ub”. These gates can be used to minimize the active power of a digital CMOS circuit by a path balancing and glitch filtering techniques discussed in recent publications. In this paper, we describe transistor sizing methods for three types of VID gates that satisfy given delay requirements. The three ways to obtain the differential delays are capacitance manipulation, nMOS transistor insertion, and CMOS transmission gate insertion. We also describe techniques for calculating the ub of each VID gate type. Finally, we outline an algorithm for quick determination of the transistor sizes for a gate for a given load capacitance. 1