This paper presents a new low-cost fault diagnosis technique based on Built-in Self Test (BIST). The method enables rapid and accurate identification of weak spots in a design and potential problems in the manufacturing process, thereby leading to a significant reduction in time-tomarket. Fault diagnosis is accelerated with available onchip BIST which can generate low-cost signatures (performance parameters). Imperfect signatures due to limited onchip resources and accuracy are compensated in two ways. Supplemental signatures are obtained from a re-configured Device Under Test (DUT) by parameter tuning, leading to improvements in diagnosability. Secondly, diagnosis accuracy is significantly improved by using an ensemble method which has been widely used in data mining. The technique can be used to identify single as well as multiple faults, and can also be used to facilitate a self-repair mechanism by accurately identifying the source of errors. Simulation results are presented to validate the technique. 1

We present a new methodology for fast analog circuit synthesis, based on the use of parameterized layout generators and symbolic performance models (SPMs) in the synthesis loop. Fast layout generation is achieved by using efficient parameterized procedural layout generators. Fast performance estimation is achieved by using pre-compiled SPMs, stored as efficient DDD-like structures called Element Coefficient Diagrams. Techniques have been developed to include layout geometry effects in the SPMs. The accuracy and efficiency of the parasitic inclusion technique as well as the proposed methodology have been demonstrated by comparisons to traditional synthesis methods. The proposed methodology is used for the synthesis of opamps and filters and is demonstrated to achieve effective performance closure. 1.

doi:10.3906/elk-1007-652 Application of asymmetrical periodic signals as test vectors for analog fault detection: a novel perspective of classical concepts