Efficiently producing default orthogonal IEEE double results using extended IEEE hardware,” Talk at 3rd Meeting of the Java Study Group (1998)

by R Golliver
Venue:JACOBI AND BERG
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Formal Verification of the VAMP Floating Point Unit

by Christoph Berg, Christian Jacobi - In CHARME 2001, volume 2144 of LNCS , 2001
"... We report on the formal verification of the floating point unit used in the VAMP processor. The FPU is fully IEEE compliant, and supports denormals and exceptions in hardware. The supported operations are addition, subtraction, multiplication, division, comparison, and conversions. The hardware is v ..."
Abstract - Cited by 9 (6 self) - Add to MetaCart
We report on the formal verification of the floating point unit used in the VAMP processor. The FPU is fully IEEE compliant, and supports denormals and exceptions in hardware. The supported operations are addition, subtraction, multiplication, division, comparison, and conversions. The hardware is verified on the gate level against a formal description of the IEEE standard by means of the theorem prover PVS.