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**11 - 19**of**19**### Ultra Low Energy CMOS Logic Using Below-Threshold Dual-Voltage Supply

, 2011

"... This paper investigates subthreshold voltage operation of digital circuits. Starting from the previously known single supply voltage for minimum energy per cycle, we further lower the energy consumption by using dual subthreshold supplies. Level converters, commonly used in the above threshold desig ..."

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This paper investigates subthreshold voltage operation of digital circuits. Starting from the previously known single supply voltage for minimum energy per cycle, we further lower the energy consumption by using dual subthreshold supplies. Level converters, commonly used in the above threshold design, are found to be unacceptably slow for subthreshold voltage operation. Therefore, special constraints are used to eliminate level converters. We give a new mixed integer linear program (MILP) that automatically and optimally assigns gate voltages, avoids the use of level converters, and holds the minimum critical path delay, while minimizing the total energy per cycle. Using examples of a 16-bit ripple-carry adder and a 4 × 4 multiplier we show energy savings of 23 % and 5%, respectively. The latter is a worst case example because most paths are critical. Alternatively, for the same energy as that of single below-threshold supply, an optimized dual voltage design can operate at 3 to 4 times higher clock rate. Also, we show energy saving up to 22.2 % from the minimum energy point over ISCAS’85 benchmark circuits. The MILP optimization with special consideration for level converters is general and applicable to any supply voltage range.

### Low Power VLSI . . .

, 2010

"... These papers focus on the development of low power VLSI design methodology on system level modeling and circuit level modeling for power optimization. The developed transition optimization approach further merged with circuit level power optimization using Glitch minimization technique. A resistive ..."

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These papers focus on the development of low power VLSI design methodology on system level modeling and circuit level modeling for power optimization. The developed transition optimization approach further merged with circuit level power optimization using Glitch minimization technique. A resistive feed back method is developed for the elimination of glitches in the CMOS circuitry, which result in power consumption and reducing performance of VLSI design. The optimized sequence is then processed through a 8-bit register bank modeled in CMOS level for data transfer to observe the glitch effect. Tanner EDA tool is used for the designing of the CMOS circuitry with resistive feedback mechanism for power optimization.

### Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation

, 2008

"... Compared to subthreshold leakage, dynamic power is normally much less sensitive to the process variation due to its approximately linear relation to the process parameters. However, the average dynamic power of a circuit optimized by a deterministic path balancing approach increases because the filt ..."

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Compared to subthreshold leakage, dynamic power is normally much less sensitive to the process variation due to its approximately linear relation to the process parameters. However, the average dynamic power of a circuit optimized by a deterministic path balancing approach increases because the filtered glitches randomly start reappearing under the influence of process variation. Combining several existing techniques, we propose a new statistical mixed integer linear programming (MILP) formulation, which uses path balancing and dual-threshold techniques to statistically minimize the total power in glitch-free circuits considering process variation.

### Signature of Author Date of Graduation

, 2007

"... Except where reference is made to the work of others, the work described in this dissertation is my own or was done in collaboration with my advisory committee. This dissertation does not include proprietary or classified information. Certificate of Approval: ..."

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Except where reference is made to the work of others, the work described in this dissertation is my own or was done in collaboration with my advisory committee. This dissertation does not include proprietary or classified information. Certificate of Approval:

### Licensed Under Creative Commons Attribution CC BY Dynamic Power Reduction in CMOS Logic Circuits using VID Technique

"... Abstract: VID is a new technique for complementary metal-oxide semiconductor (CMOS) gate design that has different delays along various inputs to output paths within the gate. Here demonstrate the use of the variable input delay CMOS gates for a totally glitch-free minimum dynamic power implementati ..."

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Abstract: VID is a new technique for complementary metal-oxide semiconductor (CMOS) gate design that has different delays along various inputs to output paths within the gate. Here demonstrate the use of the variable input delay CMOS gates for a totally glitch-free minimum dynamic power implementations of digital circuits. We obtained a power saving of 58 % over an un-optimized design. The optimized circuits had the same critical path delays as their original un-optimized versions. Since the overall delay was not allowed to increase, the glitch elimination with conventional gates required insertion of delay buffers on noncritical paths. The use of the variable

### Printed in the United States of America CMOS Leakage and Glitch Minimization for Power-Performance Tradeoff

, 2006

"... A mixed integer linear programming (MILP) technique simultaneously minimizes the leakage and glitch power consumption of a static CMOS circuit for any specified input to output delay. Using dual-threshold devices the number of high-threshold devices is maximized and a minimum number of delay element ..."

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A mixed integer linear programming (MILP) technique simultaneously minimizes the leakage and glitch power consumption of a static CMOS circuit for any specified input to output delay. Using dual-threshold devices the number of high-threshold devices is maximized and a minimum number of delay elements are inserted to reduce the differential path delays below the inertial delays of incident gates. The key features of the method are that the constraint set size for the MILP model is linear in the circuit size and power-performance tradeoff is allowed. Experimental results show 96%, 40%, and 70 % reductions of leakage power, dynamic power, and total power, respectively, for the benchmark circuit C7552 implemented in the 70 nm BPTM CMOS technology.

### Printed in the United States of America Transistor Sizing of Logic Gates to Maximize Input Delay Variability

, 2005

"... The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the delay of the gate. A conventional multi-input CMOS gate is designed to have the same input to output delay irrespective of which input caused the output to change. A gate which can offer differe ..."

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The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the delay of the gate. A conventional multi-input CMOS gate is designed to have the same input to output delay irrespective of which input caused the output to change. A gate which can offer different delays for different input-output paths through it, is known as a variable input delay (VID) gate and the maximum difference in delays of any two paths through the gate is known as “ub. ” The VID gates have a known application in minimizing the active power of a digital CMOS circuit. A previous publication has proposed three different designs for implementing VID gates. In this paper, we describe transistor sizing methods to implement the three types of VID gates for any specified delay requirement. We also describe techniques for calculating the ub for each type of gate design. We outline an algorithm for an efficient determination of the transistor sizes for a gate for given delays and output load capacitance. The algorithm is a two-step approach with a look-up table of sizes in the first stage and a sensitivity based steepest descent method for the second stage. We also give a brief introduction to the power saving potential by maximizing ub when used in conjunction with the previously published technique.

### A Technique to Reduce Glitch Power during Physical Design Stage for Low Power and Less IR Drop Vasantha Kumar B.V.P

"... A glitch compensation methodology is proposed in this paper which involves in reducing the undesired switching of combinational circuits in order to save dynamic power. The proposed methodology can be seamlessly integrated to existing physical design flow to reduce the glitch power which is one of t ..."

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A glitch compensation methodology is proposed in this paper which involves in reducing the undesired switching of combinational circuits in order to save dynamic power. The proposed methodology can be seamlessly integrated to existing physical design flow to reduce the glitch power which is one of the major contributing factors for both dynamic and IR drop. A glitch is an undesired transition that occurs before intended value in digital circuits. A glitch occurs in CMOS circuits when differential delay at the inputs of a gate is greater than inertial delay, which results into notable amount of power consumption. The glitch power is becoming more prominent in lower technology nodes. Introduction of buffers at the input of the Logic gate may reduce glitches, but it results into large area overhead and