Abstract. This paper presents a novel technique, which uses integer linear programming (ILP) to minimize the leakage power in a dual-threshold static CMOS circuit by optimally placing high-threshold devices and simultaneously reduces the glitch power using the smallest number of delay elements to balance path delays. The constraint set size for the ILP model is linear in the circuit size. Experimental results show 96%, 40 % and 70 % reduction of leakage, dynamic and total power, respectively, for the benchmark circuit C7552 implemented in the 70nm BPTM CMOS technology. 1

Abstract{A new low-power design method produces CMOS circuits that consume the least dynamic power at the highest speed permitted under the technology constraint. A gate is characterized by an inertial delay and separate delays between its inputs and output. The technology constraint, related tofeasible ranges of lengths and widths of transistors, is speci ed bya parameter u b.Itistheupper bound on the di erence between the input to output delays corresponding to any pair of inputs of a gate. We formulate a linear program (LP) whose size is proportional to the circuit size. This LP determines the inertial delay as well as input to output delays for each gate of the circuit with the given u b, such that all glitches are eliminated and the overall delay of the circuit is minimized. Because of the additional exibility in specifying gate delays, the glitch suppression is guaranteed without any delay bu ers. Hence this design consumes less power than those designed by other methods. We designed the circuit c1355 with 46 % of the original power dissipation compared toareference design. A previously published method, that characterizes each gate with a single delay, produced a c1355 circuit consuming 58% of the original power. Both low-power circuits had the same overall delay. The previous design required 224 delay bu ers, whereas the new design needed none. 1.

Abstract—This paper presents a method for minimum energy digital CMOS circuit design using dual subthreshold supply voltages. Stringent energy budget and moderate speed requirements of some ultra low power systems may not be best satisfied just by scaling a single supply voltage. Optimized circuits with dual supply voltages provide an opportunity to resolve these demands. The delay penalty of a traditional level converter is unacceptably high when the voltages are in the subthreshold range. In the present work level converters are not used and special multiple logic-level gates are used only when, after accounting for their cost, they offer advantage. Starting from a lowest per cycle energy design whose single supply voltage is in the subthreshold range, a new mixed integer linear program (MILP) finds a second lower supply voltage optimally assigned to gates with time slack. The MILP accounts for the energy and delay characteristics of logic gates interfacing two different signal levels. New types of linearized AND and OR constraints are used in this MILP. We show energy saving up to 24.5 % over the best available designs of ISCAS’85 benchmark circuits. Keywords — Ultra-low power design, Subthreshold circuits, Dual voltage design, Mixed integer linear program.

This paper investigates subthreshold voltage operation of digital circuits. The minimum energy per cycle operating point with a single voltage for this mode is known. We further lower the energy per cycle below that point by using dual subthreshold supplies. We call this the true minimum. Special considerations are used in the design for eliminating level converters. We give new mixed integer linear programs (MILP) that automatically and optimally assign gate voltages, avoid the use of level converters, and determine and hold the minimum critical path delay, while minimizing the total energy per cycle. Using examples of a 16-bit ripple-carry adder and a 4 × 4 multiplier we show energy savings of 23 % and 5%, respectively. The latter is a worst case example because most paths are critical. Alternatively, for the same energy as that of single below-threshold supply, an optimized dual voltage design can operate at 3 to 4 times higher clock rate. The MILP optimization with special consideration for level converters is general and applicable to any supply voltage range.

Abstract. The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the output delay of the gate. A conventional multi-input CMOS gate is designed to have the same input to output delay irrespective of which input caused the output to change. A gate which can offer different delays for different input-output paths through it, is known as a v ¯ ariable input delay(VID) gate and the maximum difference in delay between any two paths through the same gate is known as “ub”. These gates can be used for minimizing the active power of a digital CMOS circuit using a previosuly described technique called v ¯ ariable input delay(VID) logic. This previous publication proposed three different designs for implementating the VID gate. In this paper, we describe a technique for transistor sizing of these three flavors of the VID gate for a given delay requirement. We also describe techniques for calculating the ub of each flavor. We outline an algorithm for quick determination of the transistor sizes for a gate for a given load capacitance. 1

Modern digital circuits consist of logic gates implemented in the complementary metal oxide semiconductor (CMOS) technology. The time taken for a logic gate output to change after one or more inputs have changed is called the delay of the gate. A conventional CMOS gate is designed to have the same input to output delay irrespective of which input caused the output to change. We propose a new gate design that has different delays along various input to output paths within the gate. This is accomplished by inserting selectively sized “permanently on ” series transistors at the inputs of the logic gate. We demonstrate the use of the variable input delay CMOS gates for a totally glitch-free minimum dynamic power implementation of a digital circuit. Applying a previously described linear programming method to the c7552 benchmark circuit, we obtained a power saving of 58 % over an unoptimized design. This power consumption was 18% lower than that for an alternative low power design using conventional CMOS gates. All circuits had the same overall delay. Since the overall delay was not allowed to increase, the glitch elimination with conventional gates required insertion of delay buffers on non-critical paths. The use of the variable input delay gates drastically reduced the required number of delay buffers. 1

A gate that offers different delays for different input-output paths through it, is known as a variable input delay (VID) gate. The upper bound on this differential delay capability is specified by the parameter “ub”. These gates can be used to minimize the active power of a digital CMOS circuit by a path balancing and glitch filtering techniques discussed in recent publications. In this paper, we describe transistor sizing methods for three types of VID gates that satisfy given delay requirements. The three ways to obtain the differential delays are capacitance manipulation, nMOS transistor insertion, and CMOS transmission gate insertion. We also describe techniques for calculating the ub of each VID gate type. Finally, we outline an algorithm for quick determination of the transistor sizes for a gate for a given load capacitance. 1

Compared to subthreshold leakage, dynamic power is normally much less sensitive to the process variation due to its approximately linear relation to the process parameters. However, the average dynamic power of a circuit optimized by deterministic glitch elimination (using hazard filtering and path balancing) increases because glitches randomly start reappearing under the influence of process variation. Combining existing techniques, we propose a new statistical mixed integer linear programming (MILP) formulation, which combines glitch elimination and dual-threshold design to statistically minimize the total power in a glitch-free circuit under process variation. 1.

Compared to subthreshold leakage, dynamic power is normally much less sensitive to the process variation due to its approximately linear relation to the process parameters. However, the average dynamic power of a circuit optimized by a deterministic path balancing approach increases because the filtered glitches randomly start reappearing under the influence of process variation. Combining several existing techniques, we propose a new statistical mixed integer linear programming (MILP) formulation, which uses path balancing and dual-threshold techniques to statistically minimize the total power in glitch-free circuits considering process variation. 1.

The power dissipated in a CMOS circuit consists of dynamic power, leakage power and short-circuit power components. The topic of this paper is the reduction of dynamic power. When an input vector is applied to the primary inputs (PI), the minimum power requirement for each gate output is to produce