modulator oversampling at 16 X is implemented in a 0.72 "m complementary metal–oxide–semiconductor process for use in the baseband path of a radio-frequency receiver. The modulator achieves 77 dB of dynamic range and dissipates 81 mW from a 3.3 V supply. It is characterized for the blocking and intermodulation requirements of a cordless telephone application. Index Terms—Analog–digital conversion, radio receivers, sampled-data circuits, sigma–delta modulation, switched-capacitor circuits. I.

The power dissipation of an analog-to-digital converter (ADC) is a function of many variables, such as sampling rate (f S), resolution, architecture, process, voltage supply and technology. This chapter will attempt to establish the power dependence on sampling rate and resolution as its primary goal. To make this tenable, the scope of this task will be nar-rowed in the following two ways: 1. Architectures: Only those ADC’s suitable for use in high-speed signal processing applications, i.e., capable of attaining high Nyquist sampling rates, such as Flash, Two-step, Subranging, Folding, Interpolating and Pipelined architectures will be considered. 2. Process: Coverage will be restricted to high-integration capable IC processes such as bipolar, BiCMOS and CMOS processes which allow embedding of the ADC function in a monolithic signal processing chip. Even with a narrower scope, only a first-order analysis is attempted in light of the many variables that influence the power of an ADC. After developing power relationships for the above A/D architectures, the results of this analysis will be used to estimate the power 1 High-Speed ADC Architectures 2 variation in three high-speed system examples. 2.1 High-Speed ADC Architectures Before describing each architecture type, data gathered from published research of these types of ADC’s is presented for reference. In Fig.2-1, the resolution of the ADC’s is