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Dynamically Managing Processor Temperature and Power
 IN 2ND WORKSHOP ON FEEDBACKDIRECTED OPTIMIZATION
, 1999
"... Hardware designers are facing the following dilemma: they must ensure that the processor temperature will never exceed a safe maximum, but they also know that this maximum is reached only under unrealistic benchmarks. In other words, the processor could be more ef cient for an average workload. Mai ..."
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Cited by 60 (0 self)
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Hardware designers are facing the following dilemma: they must ensure that the processor temperature will never exceed a safe maximum, but they also know that this maximum is reached only under unrealistic benchmarks. In other words, the processor could be more ef cient for an average workload. Maintaining a safe temperature bound is made dicult because it depends on system statistics as well as external parameters such as the room temperature. We present
Interconnectpower Dissipation in a Microprocessor
 in Proceedings of the International Workshop on SystemLevel Interconnect Prediction
, 2004
"... Interconnect power is dynamic power dissipation due to switching of interconnection capacitances. This paper describes the characterization of interconnect power in a stateoftheart highperformance microprocessor designed for power efficiency. The analysis showed that interconnect power is over 5 ..."
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Cited by 49 (4 self)
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Interconnect power is dynamic power dissipation due to switching of interconnection capacitances. This paper describes the characterization of interconnect power in a stateoftheart highperformance microprocessor designed for power efficiency. The analysis showed that interconnect power is over 50 % of the dynamic power. Over 90 % of the interconnect power is consumed by only 10 % of the interconnections. Relations of interconnect power to wire length distribution and hierarchy level of nets were examined. In light of the results, a router’s algorithms were modified, to use larger wire spacing and minimal length routing for the high power consuming interconnects. The poweraware router algorithm was tested on synthesized blocks, demonstrating average saving of 14 % in the dynamic power consumption without timing degradation or area increase. The results demonstrate the obtainable benefits of tuning physical design algorithms to save power.
A 175mV MultiplyAccumulate Unit Using an Adaptive Supply Voltage and Body Bias Architecture
 IEEE J. SolidState Circuits
, 2002
"... In order to minimize total active power consumption in digital circuits, one must take into account subthreshold leakage currents that grow exponentially as technology scales. This research develops a theoretical model to predict how dynamic power and subthreshold power must be balanced to give an o ..."
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Cited by 47 (2 self)
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In order to minimize total active power consumption in digital circuits, one must take into account subthreshold leakage currents that grow exponentially as technology scales. This research develops a theoretical model to predict how dynamic power and subthreshold power must be balanced to give an optimal operating point that minimizes total active power consumption for different workload and operating conditions. A 175mV multiplyaccumulate test chip using a triplewell technology with tunable supply and body bias values is measured to experimentally verify the tradeoffs between the various sources of power. The test chip shows that there is an optimum operating point, although it differs from the theoretical limit because of excessive forward bias currents. Finally, we propose a preliminary automatic supply and body biasing architecture (ASB) that automatically configures a circuit to operate with the lowest possible active power consumption.
Variable supplyvoltage scheme for lowpower highspeed CMOS digital design
 IEEE J. SolidState Circuits
, 1998
"... Abstract—This paper describes a variable supplyvoltage (VS) scheme. From an external supply, the VS scheme automatically generates minimum internal supply voltages by feedback control of a buck converter, a speed detector, and a timing controller so that they meet the demand on its operation freque ..."
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Cited by 44 (1 self)
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Abstract—This paper describes a variable supplyvoltage (VS) scheme. From an external supply, the VS scheme automatically generates minimum internal supply voltages by feedback control of a buck converter, a speed detector, and a timing controller so that they meet the demand on its operation frequency. A 32b RISC core processor is developed in a 0.4 m CMOS technology which optimally controls the internal supply voltages with the VS scheme and the threshold voltages through substrate bias control. Performance in MIPS/W is improved by a factor of more than two compared with its conventional CMOS design. Index Terms—Buck converter, low power CMOS circuits, low threshold voltage, low voltage. I.
State assignment for Low Power Dissipation
 IEEE Journal of Solid State Circuits
, 1995
"... In this paper we address the problem of reducing the power dissipated by synchronous sequential circuits. We target the reduction of the average switching activity of the input and output state variables by minimizing the number of bit changes during state transitions. Using a probabilistic descript ..."
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Cited by 39 (5 self)
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In this paper we address the problem of reducing the power dissipated by synchronous sequential circuits. We target the reduction of the average switching activity of the input and output state variables by minimizing the number of bit changes during state transitions. Using a probabilistic description of the finite state machines, we propose a state assignment algorithm that minimizes the Boolean distance between the codes of the states with high transition probability. We formulate a general theoretic framework for the solution of the state assignment problem, and propose different algorithms trading off computational effort for quality. We then generalize our model to take into account the estimated area of a multilevel implementation during state assignment, in order to obtain final circuits where the total power dissipation is minimized. A heuristic algorithm has been implemented and applied to standard benchmarks, resulting in a 16% average reduction in switching activity. 1 Intr...
HighEfficiency LowVoltage DCDC Conversion for Portable Applications
, 1998
"... Motivated by emerging portable applications that demand ultralowpower hardware to maximize battery runtime, highefficiency lowvoltage DCDC conversion is presented as a key lowpower enabler. Recent innovations in lowpower digital CMOS design have assumed that the supply voltage is a free vari ..."
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Cited by 38 (1 self)
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Motivated by emerging portable applications that demand ultralowpower hardware to maximize battery runtime, highefficiency lowvoltage DCDC conversion is presented as a key lowpower enabler. Recent innovations in lowpower digital CMOS design have assumed that the supply voltage is a free variable and can be set to any arbitrarily low level with little penalty. This thesis introduces and demonstrates an array of DCDC converter design techniques which make this assumption more viable. The primary design challenges to highefficiency lowvoltage DCDC converters are summarized. Design techniques at the power delivery system, individual control system, and circuit levels are described which help meet the stringent requirements imposed by the portable environment. Design equations and closedform expressions for losses are presented. Special design considerations for the key dynamic voltage scaling enabler, called the dynamic DCDC converter are given. The focus throughout is on lowpower portable applications, where small size, low cost, and high energy efficiency are the primary design objectives. The design
Methods for True EnergyPerformance Optimization
, 2004
"... This paper presents methods for efficient energyperformance optimization at the circuit and microarchitectural levels. The optimal balance between energy and performance is achieved when the sensitivity of energy to a change in performance is equal for all the design variables. The sensitivitybase ..."
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Cited by 31 (12 self)
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This paper presents methods for efficient energyperformance optimization at the circuit and microarchitectural levels. The optimal balance between energy and performance is achieved when the sensitivity of energy to a change in performance is equal for all the design variables. The sensitivitybased optimizations minimize energy subject to a delay constraint. Energy savings of about 65% can be achieved without delay penalty with equalization of sensitivities to sizing, supply, and threshold voltage in a 64bit adder, compared to the reference design sized for minimum delay. Circuit optimization is effective only in the region of about 30% around the reference delay; outside of this region the optimization becomes too costly either in terms of energy or delay. Using optimal energydelay tradeoffs from the circuit level and introducing more degrees of freedom, the optimization is hierarchically extended to higher abstraction layers. We focus on the microarchitectural optimization and demonstrate that the scope of energyefficient optimization can be extended by the choice of circuit topology or the level of parallelism. In a 64bit ALU example, parallelism of five provides a threefold performance increase, while requiring the same energy as the reference design. Parallel or timemultiplexed solutions significantly affect the area of their respective designs, so the overall design cost is minimized when optimal energyarea tradeoff is achieved.
Toward Achieving Energy Efficiency in Presence of Deep Submicron Noise
 IEEE TRANSACTIONS ON VLSI SYSTEMS
, 2000
"... Presented in this paper are 1) informationtheoretic lower bounds on energy consumption of noisy digital gates and 2) the concept of noise tolerance via coding for achieving energy efficiency in the presence of noise. In particular, lower bounds on a) circuit speed and supply voltage ; b) transition ..."
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Cited by 27 (1 self)
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Presented in this paper are 1) informationtheoretic lower bounds on energy consumption of noisy digital gates and 2) the concept of noise tolerance via coding for achieving energy efficiency in the presence of noise. In particular, lower bounds on a) circuit speed and supply voltage ; b) transition activity in presence of noise; c) dynamic energy dissipation; and d) total (dynamic and static) energy dissipation are derived. A surprising result is that in a scenario where dynamic component of power dissipation dominates, the supply voltage for minimum energy operation ( ) is greater than the minimum supply voltage ( min ) for reliable operation. We then propose noise tolerance via coding to approach the lower bounds on energy dissipation. We show that the lower bounds on energy for an offchip I/O signaling example are a factor of 24 below present day systems. A very simple Hamming code can reduce the energy consumption by a factor of 3 , while ReedMuller (RM) codes give a 4 reduction in energy dissipation.
Automatic Synthesis of Gated Clocks for Power Reduction in Sequential Circuits
 IEEE Design and Test of Computers
, 1994
"... With the proliferation of portable devices and increasing levels of chip integration, reducing power consumption is becoming of paramount importance. We describe a technique to automatically synthesize gated clocks for finitestate machines (FSMs) to reduce power in the final implementation. This te ..."
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Cited by 24 (7 self)
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With the proliferation of portable devices and increasing levels of chip integration, reducing power consumption is becoming of paramount importance. We describe a technique to automatically synthesize gated clocks for finitestate machines (FSMs) to reduce power in the final implementation. This technique recognizes selfloops in the FSM (either from the state diagram or from a synchronous network) and uses the function described by the selfloops to gate the clock. The clock activation function is then used as don'tcare information to minimize the logic in the FSM for additional power savings. We applied these techniques to standard MCNC benchmarks and found an average reduction in power dissipation of 25%, at the cost of a 5% increase in area. 1 Introduction As portable devices proliferate and device sizes continue to shrink, allowing more devices to fit on a chip, power consumption has taken on increased importance. Much recent work has focused on accurate estimation of power co...
Methods for true power minimization
 in ICCAD
, 2002
"... This paper presents methods for efficient power minimization at circuit and microarchitectural levels. The potential energy savings are strongly related to the energy profile of a circuit. These savings are obtained by using gate sizing, supply voltage, and threshold voltage optimization, to minimi ..."
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Cited by 21 (6 self)
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This paper presents methods for efficient power minimization at circuit and microarchitectural levels. The potential energy savings are strongly related to the energy profile of a circuit. These savings are obtained by using gate sizing, supply voltage, and threshold voltage optimization, to minimize energy consumption subject to a delay constraint. The true power minimization is achieved when the energy reduction potentials of all tuning variables are balanced. We derive the sensitivity of energy to delay for each of the tuning variables connecting its energy saving potential to the physical properties of the circuit. This helps to develop understanding of optimization performance and identify the most efficient techniques for energy reduction. The optimizations are applied to some examples that span typical circuit topologies including inverter chains, SRAM decoders, and adders. At a delay of 20 % larger than the minimum, energy savings of 40 % to 70 % are possible, indicating that achieving peak performance is expensive in terms of energy. Energy savings of about 50 % can be achieved without delay penalty with the balancing of sizes, supplies, and thresholds. 1.