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23
VLSI cell placement techniques
 ACM Computing Surveys
, 1991
"... VLSI cell placement problem is known to be NP complete. A wide repertoire of heuristic algorithms exists in the literature for efficiently arranging the logic cells on a VLSI chip. The objective of this paper is to present a comprehensive survey of the various cell placement techniques, with emphasi ..."
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Cited by 74 (0 self)
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VLSI cell placement problem is known to be NP complete. A wide repertoire of heuristic algorithms exists in the literature for efficiently arranging the logic cells on a VLSI chip. The objective of this paper is to present a comprehensive survey of the various cell placement techniques, with emphasis on standard ce11and macro
The time complexity of maximum matching by simulated annealing
 Journal of the ACM
, 1988
"... The random, heuristic search algorithm called simulated annealing is considered for the problem of finding a maximum cardinality matching in a graph. A basic form of the algorithm is shown to produce matchings with nearly maximum cardinality such that the average time required grows as a polynomial ..."
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Cited by 51 (0 self)
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The random, heuristic search algorithm called simulated annealing is considered for the problem of finding a maximum cardinality matching in a graph. A basic form of the algorithm is shown to produce matchings with nearly maximum cardinality such that the average time required grows as a polynomial in the number of nodes in the graph. In contrast, it is also shown that for a certain family of graphs, neither the basic annealing algorithm, nor any other algorithm in a fairly large related class of algorithms, can find maximum cardinality matchings in polynomial average time.
Using simulated annealing to design good codes
 IEEE Trans. Inf. Theor
, 1987
"... AbsfructSimulated annealing is a computational heuristic for obtaining approximate solutions to combinatorial optimization problems. It is used to construct good source codes, errorcorrecting codes, and spherical codes. For certain sets of parameters codes that are better than any other known in ..."
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Cited by 41 (0 self)
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AbsfructSimulated annealing is a computational heuristic for obtaining approximate solutions to combinatorial optimization problems. It is used to construct good source codes, errorcorrecting codes, and spherical codes. For certain sets of parameters codes that are better than any other known in the literature are found. A I.
A Survey on MultiNet Global Routing for Integrated Circuits
 Integration, the VLSI Journal
, 2001
"... This paper presents a comprehensive survey on global routing research over about the last two decades, with an emphasis on the problems of simultaneously routing multiple nets in VLSI circuits under various design styles. The survey begins with a coverage of traditional approaches such as sequential ..."
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Cited by 24 (2 self)
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This paper presents a comprehensive survey on global routing research over about the last two decades, with an emphasis on the problems of simultaneously routing multiple nets in VLSI circuits under various design styles. The survey begins with a coverage of traditional approaches such as sequential routing and ripupandreroute, and then discusses multicommodity flow based methods, which have attracted a good deal of attention recently. The family of hierarchical routing techniques and several of its variants are then overviewed, in addition to other techniques such as movebased heuristics and iterative deletion. While many traditional techniques focus on the conventional objective of managing congestion, newer objectives have come into play with the advances in VLSI technology. Specifically, the focus of global routing has shifted so that it is important to augment the congestion objective with metrics for timing and crosstalk. In the later part of this paper, we summarize the recent progress in these directions. Finally, the survey concludes with a summary of
Simulated Annealing with Extended Neighbourhood
, 1991
"... Simulated Annealing (SA) is a powerful stochastic search method applicable to a wide range of problems for which little prior knowledge is available. It can produce very high quality solutions for hard combinatorial optimization problems. However, the computation time required by SA is very large. V ..."
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Cited by 21 (14 self)
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Simulated Annealing (SA) is a powerful stochastic search method applicable to a wide range of problems for which little prior knowledge is available. It can produce very high quality solutions for hard combinatorial optimization problems. However, the computation time required by SA is very large. Various methods have been proposed to reduce the computation time, but they mainly deal with the careful tuning of SA's control parameters. This paper first analyzes the impact of SA's neighbourhood on SA's performance and shows that SA with a larger neighbourhood is better than SA with a smaller one. The paper also gives a general model of SA, which has both dynamic generation probability and acceptance probability, and proves its convergence. All variants of SA can be unified under such a generalization. Finally, a method of extending SA's neighbourhood is proposed, which uses a discrete approximation to some continuous probability function as the generation function in SA, and several impo...
The Complexity of Design Automation Problems
 Advanced Semiconductor Technology and Computer Systems
, 1980
"... This paper reviews several problems that arise in the area of design automation. Most of these problems are shown to be NPhard. Further, it is unlikely that any of these problems can be solved by fast approximation algorithms that guarantee solutions that are always within some fixed relative error ..."
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Cited by 13 (0 self)
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This paper reviews several problems that arise in the area of design automation. Most of these problems are shown to be NPhard. Further, it is unlikely that any of these problems can be solved by fast approximation algorithms that guarantee solutions that are always within some fixed relative error of the optimal solution value. This points out the importance of heuristics and other tools to obtain algorithms that perform well on the problem instances of interest.
Wiring Space and Length Estimation in TwoDimensional Arrays
 IEEE Trans. on CAD
, 2000
"... We propose a new global routing area estimation approach for highperformance very large scale integration and multichip modules (MCM's). The objective is to route nets with minimum density of global cells, producing a fourbend routing for each twoterminal net. We propose an approximate upper boun ..."
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Cited by 5 (0 self)
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We propose a new global routing area estimation approach for highperformance very large scale integration and multichip modules (MCM's). The objective is to route nets with minimum density of global cells, producing a fourbend routing for each twoterminal net. We propose an approximate upper bound on global cell 2 log( (2 )), in an twodimensional array, where is the estimated lowerbound density. The total wirelength is (2 + )4 3, where + =1and is the percentage of diagonal combinations and is the percentage of adjacent combinations of nets. If (this assumption holds since a good placement minimizes the longer wires), then the total wirelength is at most 2 . By counting on the adjacent and diagonal combinations separately in the cost function, 4 3 log( (4 3) ). We verified that the bound obtained are realistic in the worst case. A solution to this problem can be used for quick estimation of necessary wiring space (for standard cell array designs) and difficulty of routing (for gate...
An ILP based hierarchical global routing approach for VLSI ASIC design
, 2007
"... The use of integrated circuits in highperformance computing, telecommunications, and consumer electronics has been growing at a very fast pace. The level of integration as measured by the number of logic gates in a chip has been steadily rising due to the rapid progress in processing and intercon ..."
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Cited by 5 (2 self)
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The use of integrated circuits in highperformance computing, telecommunications, and consumer electronics has been growing at a very fast pace. The level of integration as measured by the number of logic gates in a chip has been steadily rising due to the rapid progress in processing and interconnect technology. The interconnect delay in VLSI circuits has become a critical determiner of circuit performance. As a result, circuit layout is starting to play a more important role in today’s chip designs. Global routing is one of the key subproblems of circuit layout which involves finding an approximate path for the wires connecting the elements of the circuit without violating resource constraints. In this paper, several integer programming (ILP) based global routing models are fully investigated and explored. The resulting ILP problem is relaxed and solved as a linear programming (LP) problem followed by a rounding heuristic to obtain an integer solution. Experimental results obtained show that the proposed combined WVEM (wirelength, via, edge capacity) model can optimize several global routing objectives simultaneously and effectively. In addition, several hierarchical methods are combined with the proposed flat ILP based global router to reduce the CPU time by about 66 % on average for edge capacity model (ECM).
A Clustering Algorithm using the Tabu Search Approach with Simulated Annealing
 In Data Mining IIProceedings of Second International Conference on Data Mining Methods and Databases
, 2000
"... In this paper, an algorithm for cluster generation using tabu search approach with simulated annealing is proposed. The main idea of this algorithm is to use the tabu search approach to generate nonlocal moves for the clusters and apply the simulated annealing technique to select suitable current b ..."
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Cited by 4 (0 self)
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In this paper, an algorithm for cluster generation using tabu search approach with simulated annealing is proposed. The main idea of this algorithm is to use the tabu search approach to generate nonlocal moves for the clusters and apply the simulated annealing technique to select suitable current best solution so that speed the cluster generation. Experimental results demonstrate the proposed tabu search approach with simulated annealing algorithm for cluster generation is superior to the tabu search approach with Generalised Lloyd algorithm. 1 Clustering Clustering is the process of grouping patterns into a number of clusters, each of which contains the patterns that are similar to each other in some way. The existing clustering algorithms can be simply classied into the following two categories: hierarchical clustering and partitional clustering [1]. The hierarchical clustering operates by partitioning the patterns into successively fewer structures. This method gives rise to a d...
PARALLEL ALGORITHMS FOR PLACEMENT AND ROUTING IN VLSI DESIGN
, 1991
"... The computational requirements for high quality synthesis, analysis, and verification of VLSI designs have rapidly increased with the fast growing complexity of these designs. Research in the past has focused on the development of heuristic algorithms, special purpose hardware accelerators, or paral ..."
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Cited by 2 (0 self)
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The computational requirements for high quality synthesis, analysis, and verification of VLSI designs have rapidly increased with the fast growing complexity of these designs. Research in the past has focused on the development of heuristic algorithms, special purpose hardware accelerators, or parallel algorithms for the numerous design tasks to decrease the tirn,e required for solution. In this thesis, we propose two new parallel algorithms for two VLSI synthesis tasks, standard cell placement and global routing. The first algorithm, a parallel algorithm for global routing, uses hierarchical techniques to decompose the routing problem into independent routing subproblems that are solved in parallel. Results are then presented which compare the routing quality to the results of other published global routers and which evaluate the speedups attained. The second algorithm, a parallel algorithm for cell placement and global routing, hierarchically integrates a quadrisection placement algorithrr{, a bisection placement algorithm, and the previous global routing algorithm. Unique partitioning techniques are used to decompose the various stages of the algorithm into independent tasks which can be evaluated in parallel. Finally, we present results which evaluate the various algorithm alternatives and compare the algorithm performance to other placement programs, and we present measurements on the parallel speedups available.