Low power has emerged as a principal theme in today's electronics industry. The need for low power has caused a major paradigm shift in which power dissipation is as important as performance and area. This article presents an in-depth survey of CAD methodologies and techniques for designing low power digital CMOS circuits and systems and describes the many issues facing designers at architectural, logic and physical levels of design abstraction. It reviews some of the techniques and tools that have been proposed to overcome these difficulties and outlines the future challenges that must be met to design low power, high performance systems.

This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for high-performance VLSI circuit design under the deep submicron fabrication technologies. First, we present a number of interconnect delay models and driver/gate delay models of various degrees of accuracy and efficiency which are most useful to guide the circuit design and interconnect optimization process. Then, we classify the existing work on optimization of VLSI interconnect into the following three categories and discuss the results in each category in detail: (i) topology optimization for highperformance interconnects, including the algorithms for total wire length minimization, critical path length minimization, and delay minimization; (ii) device and interconnect sizing, including techniques for efficient driver, gate, and transistor sizing, optimal wire sizing, and simultaneous topology construction, buffer insertion, buffer and wire sizing; (iii) highperfbrmance clock routing, including abstract clock net topology generation and embedding, planar clock routing, buffer and wire sizing for clock nets, non-tree clock routing, and clock schedule optimization. For each method, we discuss its effectiveness, its advantages and limitations, as well as its computational efficiency. We group the related techniques according to either their optimization techniques or optimization objectives so that the reader can easily compare the quality and efficiency of different solutions.

In this paper, we study the interconnect design problem under a distributed RC delay model. We study the impact of technology factors on the interconnect designs and present general formulations of the interconnect topology design and wiresizing problems. We show that interconnect topology optimization can be achieved by computing optimal generalized rectilinear Steiner arborescences and we present an efficient algorithm which yields optimal or near-optimal solutions. We reveal several important properties of optimal wire width assignments and present a polynomial time optimal wiresizing algorithm. Extensive experimental results indicate that our approach significantly outperforms other routing methods for high-performance IC and MCM designs. Our interconnect designs reduce the interconnection delays by up to 66% as compared to those by the best known Steiner tree algorithm. 1 Introduction As the VLSI fabrication technology reaches submicron device dimension and gigahertz frequency, ...

In this paper, we study the optimal wiresizing problem under the distributed Elmore delay model. We show that the optimal wiresizing solutions satisfy a number of interesting properties, including the separability, the monotone property, and the dominance property. Based on these properties, we develop a polynomial-time optimal wiresizing algorithm for arbitrary interconnect structures under the distributed Elmore delay model. Extensive experimental results show that our wiresizing solution reduces interconnection delay by up to 51% when compared to the uniform-width solution of the same routing topology. Furthermore, compared to the wiresizing solution based on a simpler RC delay model in [7], our wiresizing solution reduces the total wiring area by up to 28% while further reducing the interconnection delays to the timing-critical sinks by up to 12%. 1 Introduction As the VLSI fabrication technology reaches submicron device dimension and gigahertz frequency, interconnection delay has...

The minimum rectilinear Steiner tree (MRST) problem arises in global routing and wiring estimation, as well as in many other areas. The MRST problem is known to be NP-hard, and the best performing MRST heuristic to date is the Iterated 1-Steiner (I1S) method recently proposed by Kahng and Robins. In this paper we develop a straightforward, efficient implementation of I1S, achieving a speedup factor of three orders of magnitude over previous implementations. We also give a parallel implementation that achieves near-linear speedup on multiple processors. Several performance-improving enhancements enable us to obtain Steiner trees with average cost within 0.25% of optimal, and our methods produce optimal solutions in up to 90% of the cases for typical nets. We generalize I1S and its variants to three dimensions, as well as to the case where all the pins lie on k parallel planes, which arises in, e.g., multi-layer routing. Motivated by the goal of reducing the running times of our algorith...

In this paper, we present a new algorithm for standard cell global routing. The algorithm considers all of the interconnection nets simultaneously; this produces superior results since information about all of the nets is available throughout the global routing process. Wc formulate the global routing problem as one of finding the optimal spanning forest on a graph that contains all of the interconnection information. The results of an important theorems allow us to prune many non-optimal connections before the global routing process begins. This approach successfully solves the net ordering and congestion prediction problems which other approaches suffer. The new algorithm was implemented as part of the DATools system at Xerox PARC. The benchmarks from the Physical Design Workshop are used as part of the comparison suite. The new algorithm achieves up to 11% area reduction compared to the previous global routing package used in the DATools system and obtains up to 17 % reduction in the total channel density compared to the Timberwolf 4.2 package.

Advances in fabrication technology have resulted in a continual shrinkage of device dimensions. This has resulted in smaller device delays, greater resistance along interconnect wires, and a greater impact of interconnect on total system performance. These changes have driven a considerable number of studies on single-net interconnect optimization, but relatively little work has been done to integrate the results on single-net optimization with the problem of global routing and interconnect optimization for the entire circuit. In this paper, we present the DECIMATE global router for performance driven standard cell design. The router applies both interconnect topology optimization and variable-width wire sizing optimization results to the global routing problem, while maintaining routing areas that are comparable with TimberWolf Systems' well-known commercial global router. Optimal selection of interconnection structures is shown to be an NP-Hard problem; we provide a simple heuristic for the problem, and show that it is e#ective with experiments on industry benchmarks. Under the Elmore delay model, our global router produces as much as a 35# reduction in critical path delayover TimberWolf Systems' global router, while path length reductions are as large as 52#. Circuit area optimization is performed taking into accountvariably-sized wires, #xed routing topologies, and pre-existing obstacles; an improved cost function obtains as much as an 11.6# reduction in channel densityover the result in #16#.

The minimum rectilinear Steiner tree (MRST) problem arises in global routing and wiring estimation, as well as in many other areas. The MRST problem is known to be NPhard, and the best performing MRST heuristic to date is the Iterated 1-Steiner (I1S) method recently proposed by Kahng and Robins [13]. I1S achieves significantly improved averagecase performance while avoiding the worst-case examples from which other approaches suffer, yet the algorithm has heretofore lacked a practical implementation. In this paper we develop a straightforward, efficient implementation of I1S, achieving speedup factors of over 200 compared to previous implementations. We also propose a parallel implementation of I1S that achieves near-linear speedup on K processors. Extensive empirical testing confirms the viability of our approaches, which allow for the first time the benchmarking of I1S on nets containing several hundred pins. 1 Introduction The minimum rectilinear Steiner tree problem is c...

We analyze the impact of wiresizing on the performance of Elmore-based routing constructions. Whereas previous wiresizing schemes are static (i.e., they wiresize an existing topology), we introduce a new dynamic Elmore-based wiresizing technique, which uses wiresizing considerations to drive the routing construction itself. Simulations show that dynamic wiresizing affords superior performance over static wiresizing, and also avoids topological degeneracies. Moreover, dynamically-wiresized Elmore-based routing constructions significantly outperform all previous methods in term of maximum sourcesink signal delay, affording up to 77% SPICE delay improvement over traditional Steiner routing. 1 Introduction Interconnect delay has recently become a dominant concern in the design of complex, highperformance circuits, due to the scaling of VLSI technology [9] [36]. Performance-driven layout design has thus become an active area of research over the past several years, where for a giv...

We survey our recent work in the analysis and design of interconnect topologies for high-speed VLSI. Results include: a new, fast distributed RLC analysis method based on a two-pole approximation; an A-tree formulation for performance-driven interconnect; an optimal wiresizing algorithm; and new critical-path dependent routing tree algorithms. 1 Introduction Interconnection design is becoming a major concern in the design of high-speed systems, where state-of-the-art integrated circuits use submicron technology and operate at multi-giga hertz clock rates. In this range, optimization based on the traditional layout design objective, i.e. minimization of chip area, no longer suffices since the emphasis on system performance requires different consideration. For instance, the minimum Steiner tree has traditionally been the preferred interconnect topology because: (1) it uses the minimum wiring area and (2) minimum wiring area results in minimum wire capacitance, which is the dominant fac...