VLSI cell placement problem is known to be NP complete. A wide repertoire of heuristic algorithms exists in the literature for efficiently arranging the logic cells on a VLSI chip. The objective of this paper is to present a comprehensive survey of the various cell placement techniques, with emphasis on standard ce11and macro

Evolvable hardware (EHW) has attracted increasing attention since early 1990's with the advent of easily reconfigurable hardware such as field programmable gate arrays (FPGAs). It promises to provide an entirely new approach to complex electronic circuit design and new adaptive hardware. EHW has been demonstrated to be able to perform a wide range of tasks from pattern recognition to adaptive control. However, there are still many fundamental issues in EHW which remain open. This paper reviews the current status of EHW, discusses the promises and possible advantages of EHW, and indicates the challenges we must meet in order to develop practical and large-scale EHW. 1 Introduction Evolvable hardware (EHW) refers to hardware that can change its architecture and behaviour dynamically and autonomously by interacting with its environment. At present, almost all EHW uses an evolutionary algorithm (EA) as their main adaptive mechanism. One of the key motivations behind EHW is to learn from N...

Abstruct- In this paper, the convergence properties of a stochastic optimization algorithm called the stochastic evolution (SE) algorithm is analyzed. We show that a generic formulation of the SE algorithm can be modeled by an ergodic Markov chain. As such, the global convergence of the SE algorithm is established as the state transition from any initial state to the globally optimal states. We propose a new criterion called the mean first visit time (MFVT) to characterize the convergence rate of the SE algorithm. With MFVT, we are able to show analytically that on average, the SE algorithm converges faster than the random search method to the globally optimal states. This result is further confirmed using the Monte Carlo simulation. I.

This technical report is prepared to record the preliminary work carried out in beginning a research project on the solution of a group of related problems by means of Genetic Algorithms (GA's). These problems include integrated circuit layout compaction, bin packing, and nesting. The principal problem is compaction, with the others serving to illuminate and guide the compaction work, as well as possibly receiving benefits from new tools developed. Efficient and near-optimal solution of the compaction problem will enhance the linkage between symbolic level modeling of the layout and the mask level design of hierarchical (fragment-based), ultra-fast, lowpower analog and logic circuits. The research goals are to develop new methodologies, abstractions, and theory that lead to more efficiently defined and utilized Computer-Aided Design (CAD) algorithms and tools for compaction, bin packing and nesting. These new methodologies will incorporate important improvements in the handling of the physical, technological, and optimization aspects of compaction. More effective solution of the bin packing and nesting problems can help to solve the compaction problem, as well as being valuable in their own right for many practical problems. This will be accomplished by defining a new approach to the use of Genetic Algorithms (GAs)--for the compaction, bin packing, and nesting problems. The research will concentrate mostly on the application area of high-speed, low-power analog and digital circuits with clock rates up to 20 GHz. In many applications in this high performance area, dramatically reduced chip area and signal delays are important design requirements. The technology area of interest is multi-chip modules (MCM) based on current or advanced silicon and GaAs technologies [1]. Th...

The computational requirements for high quality synthesis, analysis, and verification of VLSI designs have rapidly increased with the fast growing complexity of these designs. Research in the past has focused on the development of heuristic algorithms, special purpose hardware accelerators, or parallel algorithms for the numerous design tasks to decrease the tirn,e required for solution. In this thesis, we propose two new parallel algorithms for two VLSI synthesis tasks, standard cell placement and global routing. The first algorithm, a parallel algorithm for global routing, uses hierarchical tech-niques to decompose the routing problem into independent routing subproblems that are solved in parallel. Results are then presented which compare the routing quality to the results of other published global routers and which evaluate the speedups attained. The second algorithm, a parallel algorithm for cell placement and global routing, hierarchically integrates a quadrisection placement algorithrr{, a bisection placement algorithm, and the previous global routing algorithm. Unique partitioning techniques are used to decompose the various stages of the algorithm into independent tasks which can be evaluated in parallel. Finally, we present results which evaluate the various algo-rithm alternatives and compare the algorithm performance to other placement programs, and we present measurements on the parallel speedups available.

The task of VLSI physical design is to produce the layout of an integrated circuit. New performance requirements are becoming increasingly dominant in today's sub-micron regimes requiring new physical design algorithms. Genetic algorithms have been increasingly successful when applied in VLSI physical design in the last 10 years. Genetic algorithms for VLSI physical design are reviewed in general. In addition, a specific parallel genetic algorithm is presented for the routing problem in VLSI circuits.

The design of modern integrated circuits is overwhelmingly complicated due to the enormous number of cells in a typical modern circuit. To deal with this di#culty, the design procedure is broken down into a set of disjoint tasks. Circuit layout is the task that refers to the physical realization of a circuit from its functional description. In circuit layout, a connection-list called netlist of cells and nets is given. Placement and routing are subtasks associated with circuit layout and involve determining the geometric locations of the cells within the placement area and connecting cells sharing common nets. In performing the placement and the routing of the cells, minimum placement area, minimum delay and other performance constraints need to be observed.

This paper reviews an approach to the design of composite material structures based on Genetic Algorithms. We first discuss the concept of a Genetic Algorithm (GA) and the role it can play in design, namely as an evolutionary search optimizer based on simulation results. We then discuss the composite structure design problem and how GA's can be used for design in this domain. Finally we discuss various experiments we have conducted and our results in using GA's for the design of energy absorbing composite material structures. 1 A Genetic Algorithm Approach to Design of Advanced Composite Material Structures Keywords: Design, Genetic Algorithms, Composite Material, Laminated Structure, Optimization Abstract This paper reviews an approach to the design of composite material structures based on Genetic Algorithms. We first discuss the concept of a Genetic Algorithm (GA) and the role it can play in design, namely as an evolutionary search optimizer based on simulation results....