The architectural diversity and complexity of network processor architectures motivate the need for a more natural abstraction of the underlying hardware. In this paper, we describe a programming model, NP-Click, which makes it possible to write efficient code and improve application performance without having to understand all of the details of the target architecture. Using this programming model, we implement the data plane of an IPv4 router on a particular network processor, the Intel IXP1200, and compare results with a hand-coded implementation. Our results show the IPv4 router written in NP-Click performs within 7 % of a hand-coded version of the same application using a realistic packet mix. 1.

This paper studies the usage of a reconfigurable architecture platform for embedded control applications aimed at improving real time performance. The hw/sw codesign methodology from POLIS is used. It starts from high-level specifications, optimizes an intermediate model of computation (Extended Finite State Machines) and derives both hardware and software, based on performance constraints. We study a particular architecture platform, which consists of a general purpose processor core, augmented with a reconfigurable function unit and data-path to improve run time performance. A new mapping flow and algorithms to partition hardware and software are proposed to generate implementation that best utilizes this architecture. Encouraging preliminary results are shown for automotive electronic control examples.

... This paper surveys a variety of techniques for translating these concurrent specifications into sequential code. The techniques address compiling a wide variety of languages, ranging from dataflow to Petri nets. Each uses a different technique, to some degree chosen to match the semantics of concurrent language. Each technique is considered to consist of a partial evaluator operating on an interpreter. This combination provides a clearer picture of how parts of each technique could be used in a different setting.

This paper addresses the problem of automatic generation of implementation software from high-level functional specifications in the context of embedded system on chip designs. Software design complexity for embedded systems has increased so much that a high-level functional programming paradigm need to be adopted for formal verifiability, maintainability and short time-to-market. We propose a framework for efficiently generating implementation software from a synchronous state machine specification for embedded control systems. The framework is generic enough to allow hardware/software partition for a given architecture platform. It is demonstrated that the logic optimization and simulation techniques can be combined to produce fast execution code for such embedded systems. Specifically, we propose a framework for software synthesis from multi-valued logic, including fast evaluation of logic functions, and scheduling techniques for node execution. Experiments are performed to show the initial results of our algorithms in this framework.

We propose a method of automatic generation of application specific operating systems (OS's) and automatic targeting of application software. OS generation starts from a very small but yet flexible OS kernel. OS services, which are specific to the application and deduced from dependencies between services, are added to the kernel to construct the whole OS. Communication and synchronization functions in the application code are adapted to the generated OS. As a preliminary experiment, we applied the proposed method to a system example called token ring system. 1.

Abstract. Esterel is a design language for the representation of embedded systems. Based on the synchronous reactive paradigm, its execution relies on a clear distinction of instants of computation. As a consequence, deciding whether a piece of a program may or may not run instantaneously is central to any compilation scheme, both for correctness and efficiency. In general, this information can be obtained by an exhaustive exploration of all possible execution paths, which is expensive. Most compilers approximate it through algorithmic methods amenable to static analysis. In our contribution, we first formalize the analysis involved in detecting statements that may run instantaneously. Then, we identify statements that may terminate and be instantaneously reentered. This allows us to model precisely these compilers front-end activities with a clear mathematical specification and led us to uncover inefficiencies in the Esterel v5 academic compiler from Ecole des Mines and INRIA. 1

This report presents a series of techniques for automatic specialization of generic component specifications. These techniques allow the transformation of a generic component specifications into more compact and efficient ones. We have integrated these techniques into a code generator for Ptolemy II, a software framework for actor-oriented design in Java [15]. Combining automatic code generation with actor specialization enables efficient implementation of models without sacrificing design flexibility. We call this approach to implementing an actor oriented model cocompilation, to emphasize how it integrates compiler optimization with automatic code generation. It is conceptually similar to concepts of Aspect-Oriented Design [28], since the style of component interaction is incorporated into the specification of a component

The overhead of context-switching limits efficient scheduling of multiple concurrent threads on a uniprocessor when real-time requirements exist. Existing software thread integration (STI) methods reduce context switches, but only provide synchronous thread progress within integrated functions. For the remaining, non-integrated portions of the secondary threads to run and avoid starvation, the primary thread must have adequate amounts of coarse-grain idle time (longer than two context-switches). We have developed asynchronous software thread integration (ASTI) methods which address starvation through the efficient use of coroutine calls and integration. ASTI allows threads to make independent progress efficiently and reduces the number of context switches needed through integration. Software-implemented protocol controllers are crippled by this problem; the primary thread “bit-bangs ” each bit of a message onto or off of the bus, leaving only fragments of idle time shorter than a bit time. This fragmented time may be too short to recover through context switching, so only the primary thread can execute during message transmission or reception, slowing the secondary threads and potentially making them miss their deadlines. ASTI simplifies the implementation of embedded communication protocols on low-cost, moderate speed (1- 100 MHz, 8- and 16-bit) microcontrollers. We demonstrate ASTI by replacing a standard automotive communication protocol controller (J1850) with software and generic hardware. Secondary thread performance improves significantly when compared with a traditional interrupt-based software approach.

ESP is a language for programmable devices. Unlike C which forces a tradeoff that requires giving up ease of programming and reliability to achieve high performance, ESP is designed to provide all of these three properties simultaneously. This paper measures the performance impact on applications of using ESP to implement VMMC firmware. It compares the performance of an earlier implementation of VMMC firmware that used C with the new implementation that uses ESP. We find that SPLASH2 applications incur a modest performance hit (3.5 % on average) when using the ESP version.

Abstract Synchronous languages rely on formal methods to ease the development of applications in an efficient and reusable way. Formal methods have been advocated as a means of increasing the reliability of systems, especially those which are safety or business critical. It is still difficult to develop automatic specification and verification tools due to limitations like state explosion, undecidability, etc... In this work, we design a new specification model based on a reactive synchronous approach. Then, we benefit from a formal framework well suited to perform compilation and formal validation of systems. In practice, we design and implement a special purpose language (LE) and its two semantics: the behavioral semantics helps us to define a program by the set of its behaviors and avoid ambiguousness in programs ’ interpretation; the execution equational semantics allows the modular compilation of programs into software and hardware targets (C code, Vhdl code, Fpga synthesis, Verification tools). Our approach is pertinent considering the two main requirements of critical realistic applications: the modular compilation allows us to deal with large systems, the model-driven approach provides us with formal validation. keywords: model-driven language, synchronous models, compilation, modularity, verification