Asynchronous design has enjoyed a revival of interest recently, as designers seek to eliminate penalties of traditional synchronous design. In principle, asynchronous methods promise to avoid overhead due to clock skew, worst-case design assumptions and resynchronization of asynchronous external inputs. In practice, however, many asynchronous design methods suffer from a number of problems: unsound algorithms (implementations may have hazards), harsh restrictions on the range of designs that can be handled (single-input changes only), incompatibility with existing design styles and inefficiency in the resulting circuits. This thesis presents a new locally-clocked design method for the synthesis of asynchronous controllers. The method has been automated, is proven correct and produces high-performance implementations which are hazard-free at the gate-level. Implementations allow multiple-input changes and handle a relatively unconstrained class of behaviors (called "burst-mode" specifications). The method produces state-machine implementations with a minimal or near-minimal number of states. Implementations can be easily built in such common VLSI design styles as gate-array, standard cell and full-custom. Realizations typically have the latency of

This paper describes a new method for exact hazard-free logic minimization of Boolean functions. Given an incompletely-specified Boolean function, the method produces a minimum-cost sum-ofproducts implementation which is hazard-free for a given set of multiple-input changes, if such a solution exists. The method is a constrained version of the Quine-McCluskey algorithm. It has been automated and applied to a number of examples. Results are compared with results of a comparable non-hazard-free method (espresso-exact). Overhead due to hazard-elimination is shown to be negligible.

Abstract not found

Abstract not found

This paper presents hazard-non-increasing optimization algorithms. These are optimizations on gate-level logic without introduction of any further static and dynamic hazards. Proofs are given for general theoretical results on hazard-non-increasing transformations which serve as the basis for these algorithms. The algorithms in this paper substantially augment the set of proven hazard-non-increasing optimization techniques in the literature. These algorithms are useful for hazard-free implementations of asynchronous designs.

Approved by Dissertation Committee: This thesis is dedicated to: the gift of music pizza Beef Wellington the wines of Bordeaux mi amore

We describe a new method for directly synthesizing a hazard-free multilevel logic implementation from a given logic specification. The method is based on free/ordered Binary Decision Diagrams (BDD's), and is naturally applicable to multiple-output logic functions. Given an incompletelyspecified (multiple-output) Boolean function, the method produces a multilevel logic network that is hazard-free for a specified set of multiple-input changes. We assume an arbitrary (unbounded) gate and wire delay model under a pure delay (PD) assumption, we permit multiple-input changes, and we consider both static and dynamic hazards under the fundamental-mode assumption. Our framework is thus general and powerful. While it is not always possible to generate hazard-free implementations using our technique, we show that in some cases hazard-free multilevel implementations can be generated when hazard-free two-level representations cannot be found. This problem is generally regarded as a difficult problem and it has important applications in the field of asynchronous design. The method has been automated and applied to a number of examples.

Abstract — This paper presents an automated method for the synthesis of multiple-input-change (MIC) asynchronousstate machines. Asynchronousstate machine design is subtle since, unlike synchronous synthesis, logic must be implemented without hazards, and state codes must be chosen carefully to avoid critical races. We formulate and solve an optimal hazard-freeand critical race-free encoding problem for a class of MIC asynchronousstate machines called burst-mode. Analogous to a paradigm successfully used for the optimal encoding of synchronous machines, the problem is formulated as an input encoding problem. Implementations are targeted to sum-of-product realizations. We believe this is the first general method for the optimal encoding of hazard-free MIC asynchronousstate machines under a generalized fundamental mode of operation. Results indicate that improved solutions are produced, ranging up to 17 % improvement. 1

Modern high-performance asynchronous circuits depend on timing constraints for correct operation, so timing analyzers are essential asynchronous design tools. In this paper, we present a 13-valued abstract waveform algebra and a polynomial-time min-max timing simulation algorithm for use in efficient, approximate timing analysis of asynchronous circuits with bounded component delays. Unlike several previous approaches, our algorithm computes separate propagation delay bounds from each circuit input to each internal gate. This is useful for analyzing asynchronous circuits, where the relative transition times of the inputs may not be known a priori, unlike synchronous circuits. We also describe an efficient reconvergent fanout analysis technique that helps in increasing the accuracy of simulation. We have applied our algorithm to build an efficient timing analysis tool for extended burst-mode circuits (a class of timing-dependent asynchronous circuits) implemented in the 3D design style ...

We describe an efficient timing analysis technique for extended burst-mode circuits implemented according to the 3D design style. Gate-level 3D circuits with uncertain component delays are analyzed, and safe bounds on timing constraints for correct circuit operation are computed. We employ two passes of multi-valued logic simulation to precisely identify gates where timing constraint violations manifest themselves. Signal propagationdelay bounds from the primary inputs to these gates are then used to compute global timing constraints for correct circuit operation. Timing constraints identified by our tool represent conservative approximations to the true timing requirements in the worstcase. In practice, our results are accurate on almost all of the 3D benchmarks we have experimented with. 1. Introduction As designers strive to improve the performance of hardware systems, there has been a renewed interest in asynchronous design methodologies [24, 8, 20, 19, 2, 26, 25, 16, 15]. One pr...