We present a fast but reliable way to detect routing criticalities in VLSI chips. In addition, we show how this congestion estimation can be incorporated into a partitioning based placement algorithm. Different to previous approaches, we do not rerun parts of the placement algorithm or apply a post-placement optimization, but we use our congestion estimator for a dynamic avoidance of routability problems in one single run of the placement algorithm. Computational experiments on chips with up to 1,300,000 cells are presented: The framework reduces the usage of the most critical routing edges by 9.0% on average, the running time increase for the placement is about 8.7%. However, due to the smaller congestion, the running time of routing tools can be decreased drastically, so the total time for placement and (global) routing is decreased by 47% on average.

As technology advances, more and more issues need to be considered in the placement stage, e.g., wirelength, congestion, timing, coupling. It is very hard to consider all of them together at the same time. Thus it is good if we can optimize one cost function without affecting others. In this paper, we will study methods to optimize congestion in placement without inflicting degradations/violations in other objectives or constraint. We give a mathematical equation to predict the overflow within a region using a normal distribution approximation. According to experiments, this equation does give a good estimation of overflow. We used this equation to find the smallest regions which have enough routing resource to alleviate the congestion and propose the flexible expansion scheme in our multi-center congestion reduction (MC 2 R) algorithm. Experimental results show that generally there is a correlation between the amount of reduction in congestion and the amount of change made to the pl...

Abstract—This paper presents an efficient technique for the estimation of the routed wirelength during global placement using the wire density of the net. The proposed method identifies congested regions of the chip and incorporates the model of the routed wirelength into the objective function in order to effectively alleviate these regions from congestion. The method is integrated in the analytical placement framework and the two-level structure improves the scalability of the placer and speeds up the algorithm. The proposed analytical placer provides the best-so-far average routed wirelength in the IBM version2 benchmark suite. I.

The use of integrated circuits in high-performance computing, telecommunications, and consumer electronics has been growing at a very fast pace. The level of integration as measured by the number of logic gates in a chip has been steadily rising due to the rapid progress in processing and interconnect technology. The interconnect delay in VLSI circuits has become a critical determiner of circuit performance. As a result, circuit layout is starting to play a more important role in today’s chip designs. Global routing is one of the key sub-problems of circuit layout which involves finding an approximate path for the wires connecting the elements of the circuit without violating resource constraints. In this paper, several integer programming (ILP) based global routing models are fully investigated and explored. The resulting ILP problem is relaxed and solved as a linear programming (LP) problem followed by a rounding heuristic to obtain an integer solution. Experimental results obtained show that the proposed combined WVEM (wirelength, via, edge capacity) model can optimize several global routing objectives simultaneously and effectively. In addition, several hierarchical methods are combined with the proposed flat ILP based global router to reduce the CPU time by about 66 % on average for edge capacity model (ECM).

In this paper, we provide a new efficient and accurate congestion model embedded into a floorplanner to estimate the congestion of floorplans. It is based on probabilistic analysis and a new concept of Irregular-Grid which uses the routing information to determine the evaluating regions instead of fixed-size grids. Three complete experiments are performed and the experimental results show the correctness, accuracy and efficiency of our new congestion model. 1.

As technology moves into the deep-submicron era, the complexity of VLSI circuit design grows rapidly, especially in the interconnections between modules. Therefore, interconnect optimization has become an important concern in floorplanning today. Most routability-driven floorplanners [2][6][8] use grid-based approach that divides a floorplan into grids as in global routing. Congestion is estimated as the expected number of nets passing through each grid. Although this approach is direct and accurate, it is not efficient when dealing with complex circuit containing thousands of nets. In this paper, an efficient and innovative routability-driven floorplanner using twin binary trees (TBT)[9][10] representation is proposed. The congestion model we used is the wire density on the half-perimeter boundary of different regions in a floorplan. These regions are defined naturally by the TBT representation. In order to increase the efficiency of our floorplanner, a fast algorithm for the least common ancestor (LCA) problem in [1] is used to compute the wire density. From the experimental results, the number of unroutable wires can be reduced in a short time.

Recent advances in VLSI technology have made optimization of the interconnect delay and routability of a circuit more important. We should consider interconnect planning as early as possible. We propose a postfloorplanning step to reduce the interconnect cost of a floorplan by searching alternative packings. If a packing contains a rectangular bounding box of a group of modules, we can rearrange the blocks in the bounding box to obtain a new floorplan with the same area, but possibly with a smaller interconnect cost. Experimental results show that we can reduce the interconnect cost of a packing without any penalty in area.

... proposed in this paper. With the fast feedback on congestion, FREe serves incremental placement or guides routing to shorten the physical design time. FREe firstly extends an existing combinatorial model with the extended bounding box for flat tow-pin nets/sections to pre-estimate congestion probabilistically. Then, it routes all nets guided by the pre-estimation to get more exact congestion estimation, which is fast since it does not include any iteration/optimization as a router does. The idea of FREe is net-order-independent. FREe can get a uniform usage of routing resources by probability. The experimental results show that FREe can give more detailed congestion information in a short running time. Compared FREe with a recent router SSTT, we find that FREe has a good congestion correlation with SSTT, but FREe is more objective.

As the complexity of physical implementation continues to grow with technology scaling, routability has emerged as a major concern and implementation flow bottleneck. Infeasibility of routing forces a loop back to placement, netlist optimization, or even RTL design and floorplanning. Thus, to maintain convergence and a manageable number of iterations in the physical implementation flow, it is necessary to accurately predict design routability as quickly as possible. Routability estimation during placement typically exploits rough but fast global routers. Fast global routers are integrated with placers and are supposed to provide accurate congestion estimation for each iterative placement optimization, with short turn-around time. Such integrated global routers (as well as congestion estimators without global routers) should give (1) fast, and (2) stably accurate decisions as to whether a given placement is indeed routable. In this paper, we evaluate four academic global routers [14] [1] [9] [4] in terms of stability and scalability. We perturb global routing problem instances in controlled ways, and analyze the sensitivity of routing outcomes and metrics. We observe scaling suboptimality and substantial noise in most of our experiments; this suggests a future need for new global router criteria and metrics. 1.

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