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Technology Mapping Algorithms for Domino Logic
, 2002
"... In this paper, we present an efficient algorithm for technology mapping of domino logic to a parameterized library. The algorithm is optimal for mapping trees consisting of 2input AND/OR nodes, and has a computation time that is polynomial in terms of constraint size. The mapping method is then ext ..."
Abstract

Cited by 1 (1 self)
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In this paper, we present an efficient algorithm for technology mapping of domino logic to a parameterized library. The algorithm is optimal for mapping trees consisting of 2input AND/OR nodes, and has a computation time that is polynomial in terms of constraint size. The mapping method is then extended to DAG covering that permits the implicit duplication of logic nodes. Our synthesis procedure maps the complementary logic cones independently when AND/OR logic is to be implemented, and together using dualmonotonic gates in the case of XOR/XNOR logic. The mapping procedure solves the output phase assignment problem as a preprocessing step. Based on a key observation that the output phase assignment could reduce the implementation cost due to the possible large cost di#erence between two polarities, a 01 integer linear programming formulation was formed to minimize the implementation cost. Our experimental results show the effectiveness of the proposed techniques
Estimation of layout densities for CMOS digital circuits
"... The transistor density is one of the parameters to be considered for an optimal use of CMOS process. Therefore, layout strategies have to be evaluated through metrics considering all the involved parameters. The objective of this paper is to study the real transistor density available for a given te ..."
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The transistor density is one of the parameters to be considered for an optimal use of CMOS process. Therefore, layout strategies have to be evaluated through metrics considering all the involved parameters. The objective of this paper is to study the real transistor density available for a given technology at the cell and circuit levels. This study has three main interests: (i) to evaluate the quality of the layout synthesis tools in terms of area; (ii) to give a feedback to the logic synthesis step, allowing an accurate area prediction from the gate level abstraction; and (iii) to determine a transistor density roadmap. 1. Introduction The availability of submicronic process with multilayer routing possibilities opens the way for defining new optimal layout strategies. The routing, shielding and spacing of multilevel signals must conserve signal integrity [1]. All these considerations must be used in defining layout strategies and styles of implementation. Layouts of random logi...
Timing Optimization By Gate Resizing And Critical Path Identification
 IEEE trans. On CAD of Integrated Circuits and Systems
, 1995
"... Due to the rapid progress in VLSI technology, the overall complexity of the chip has increased dramatically. There is a simultaneous need for more functions and higher speed in modern VLSI engineering. Therefore, using a minimum amount of extra hardware to meet timing requirements is becoming a majo ..."
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Due to the rapid progress in VLSI technology, the overall complexity of the chip has increased dramatically. There is a simultaneous need for more functions and higher speed in modern VLSI engineering. Therefore, using a minimum amount of extra hardware to meet timing requirements is becoming a major issue in VLSI design. Here, we propose an efficient method for timing optimization using gate resizing. To control the hardware overhead, a minimum (or as small as possible) number of gates are selected for resizing with the aid of a powerful benefit function. To guarantee the performance of timing optimization, a modified version of PODEM [1], called PODEM, ensures that each resized gate is located on at least one critical path. Thus, resizing a gate definitely reduces circuit delay. Simulation results demonstrate that our timing optimization method can efficiently reduce circuit delay with a limited amount of gate resizing. 1 1. Introduction In recent years, semiconductor technology h...
Estimation of layout densities for CMOS digital circuits
"... The transistor density is one of the parameters to be considered for an optimal use of CMOS process. Therefore, layout strategies have to be evaluated through metrics considering all the involved parameters. The objective of this paper is to study the real transistor density available for a given te ..."
Abstract
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The transistor density is one of the parameters to be considered for an optimal use of CMOS process. Therefore, layout strategies have to be evaluated through metrics considering all the involved parameters. The objective of this paper is to study the real transistor density available for a given technology at the cell and circuit levels. This study has three main interests: (i) to evaluate the quality of the layout synthesis tools in terms of area; (ii) to give a feedback to the logic synthesis step, allowing an accurate area prediction from the gate level abstraction; and (iii) to determine a transistor density roadmap. 1.
Evaluation of Transistor Densities for Submicronic CMOS Technologies
"... The transistor density is one of the parameters to be considered for an optimal use of CMOS process. Therefore, layout strategies have to be evaluated through metrics considering all the involved parameters. The objective of this paper is to study the real transistor density available for a given ..."
Abstract
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The transistor density is one of the parameters to be considered for an optimal use of CMOS process. Therefore, layout strategies have to be evaluated through metrics considering all the involved parameters. The objective of this paper is to study the real transistor density available for a given technology at the cell and circuit level, from the design rules. This study has three main consequences: (i) to evaluate the quality of the layout synthesis CAD tools in terms of area; (ii) to give a feedback to the logic synthesis step, allowing an accurate area prediction from the gate level abstraction; and (iii) to determine a transistor density roadmap. We will compare the predicted densities, for different design rules, with real layouts generated with macrocell generators and for standardcell libraries. 1.
Probabilitydriven Routing in a Datapath Environment
"... For a fourlayer datapath routing environment, we present an algorithm that considers all the nets simultaneously, thus avoiding the netordering problem. Our algorithm progresses in two phases. The first phase involves formulating the problem using a probabilistic model, whereby routing probabiliti ..."
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For a fourlayer datapath routing environment, we present an algorithm that considers all the nets simultaneously, thus avoiding the netordering problem. Our algorithm progresses in two phases. The first phase involves formulating the problem using a probabilistic model, whereby routing probabilities are calculated for potential routing regions; these probabilities are consolidated into a congestion metric for each region. The second phase employs an iterative diversion technique where the region with the maximum congestion metric is iteratively relaxed. The above process is repeated until the track probabilities crystallize into integer values of 1 and 0. We have run the algorithm on large test cases; and experimental results show that we can achieve significant routability within a few number of available tracks.