Results 1  10
of
17
Reducing Clock Skew Variability via Cross Links
 IN PROCEEDINGS OF THE 41ST ANNUAL CONFERENCE ON DESIGN AUTOMATION
, 2004
"... Increasingly significant variational e#ects present a great challenge for delivering desired clock skew reliably. Nontree clock network has been recognized as a promising approach to overcome the variation problem. Existing nontree clock routing methods are restricted to a few simple or regular ..."
Abstract

Cited by 27 (6 self)
 Add to MetaCart
Increasingly significant variational e#ects present a great challenge for delivering desired clock skew reliably. Nontree clock network has been recognized as a promising approach to overcome the variation problem. Existing nontree clock routing methods are restricted to a few simple or regular structures, and often consume excessive amount of wires. In this paper, we suggest to construct a low cost nontree clock network by inserting cross links in a given clock tree. The e#ect of the link insertion on clock skew variability is analyzed. Based on the analysis, two link insertion schemes are proposed. These methods can quickly convert a clock tree to a nontree with significantly lower skew variability and very small amount of extra wires. Further, they can be applied to the recently popular nonzero skew routing easily. Experimental results on benchmark circuits show that this approach can achieve significant skew variability reduction with less than 2% increase of wirelength.
A Timing Model Incorporating the Effect of Crosstalk on Delay and its Application to Optimal Channel Routing
, 2000
"... Crosstalk is generally recognized as a major problem in IC design. This paper presents a novel approach to the efficient measurement of the effect of crosstalk on the delay of a net using an algorithm whose worstcase complexity is polynomialtime in the number of nets. The cost of the algorithm is ..."
Abstract

Cited by 22 (0 self)
 Add to MetaCart
Crosstalk is generally recognized as a major problem in IC design. This paper presents a novel approach to the efficient measurement of the effect of crosstalk on the delay of a net using an algorithm whose worstcase complexity is polynomialtime in the number of nets. The cost of the algorithm is seen to be O(n log n) in practice, where n is the number of nets, and it is amenable to being incorporated into the inner loop of a timing optimizer. To illustrate this, the method is applied to reduce the effects of crosstalk in channel routing, whereitisseen to give an average improvement of 23% in the delay in a channel as compared to the worst case, as measured by SPICE.
Optimizing dominant time constant in RC circuits
, 1996
"... We propose to use the dominant time constant of a resistorcapacitor (RC) circuit as a measure of the signal propagation delay through the circuit. We show that the dominant time constant is a quasiconvex function of the conductances and capacitances, and use this property to cast several interestin ..."
Abstract

Cited by 16 (8 self)
 Add to MetaCart
We propose to use the dominant time constant of a resistorcapacitor (RC) circuit as a measure of the signal propagation delay through the circuit. We show that the dominant time constant is a quasiconvex function of the conductances and capacitances, and use this property to cast several interesting design problems as convex optimization problems, specifically, semidefinite programs (SDPs). For example, assuming that the conductances and capacitances are affine functions of the design parameters (which is a common model in transistor or interconnect wire sizing), one can minimize the power consumption or the area subject to an upper bound on the dominant time constant, or compute the optimal tradeoff surface between power, dominant time constant, and area. We will also note that, to a certain extent, convex optimization can be used to design the topology of the interconnect wires. This approach has two advantages over methods based on Elmore delay optimization. First, it handles a far wider class of circuits, e.g., those with nongrounded capacitors. Second, it always results in convex optimization problems for which very efficient interiorpoint methods have recently been developed. We illustrate the method, and extensions, with several examples involving optimal wire and transistor sizing.
An Efficient Method for LargeScale Gate Sizing
 IEEE Trans. on Circuits and Systems I: Fundamental Theory and Applications
"... Abstract—We consider the problem of choosing the gate sizes or scale factors in a combinational logic circuit in order to minimize the total area, subject to simple RC timing constraints, and a minimumallowed gate size. This problem is well known to be a geometric program (GP), and can be solved by ..."
Abstract

Cited by 6 (1 self)
 Add to MetaCart
Abstract—We consider the problem of choosing the gate sizes or scale factors in a combinational logic circuit in order to minimize the total area, subject to simple RC timing constraints, and a minimumallowed gate size. This problem is well known to be a geometric program (GP), and can be solved by using standard interiorpoint methods for small and mediumsize problems with up to several thousand gates. In this paper, we describe a new method for solving this problem that handles far larger circuits, up to a million gates, and is far faster. Numerical experiments show that our method can compute an adequately accurate solution within around 200 iterations; each iteration, in turn, consists of a few passes over the circuit. In particular, the complexity of our method, with a fixed number of iterations, is linear in the number of gates. A simple implementation of our algorithm can size a 10 000 gate circuit in 25 s, a 100 000 gate circuit in 4 min, and a million gate circuit in 40 min, approximately. For the million gate circuit, the associated GP has three million variables and more than six million monomial terms in its constraints; as far as we know, these are the largest GPs ever solved. Index Terms—Gate sizing, geometric programming (GP), largescale optimization. I.
An EnergyComplexity Model for VLSI Computations
, 1995
"... An energy complexity model for CSP programs to be implemented in CMOS VLSI is developed. This model predicts with some accuracy the energy dissipation of the "standard" asynchronous VLSI implementation of a CSP program, associated to a given trace of that program. This energy complexity is used in t ..."
Abstract

Cited by 5 (0 self)
 Add to MetaCart
An energy complexity model for CSP programs to be implemented in CMOS VLSI is developed. This model predicts with some accuracy the energy dissipation of the "standard" asynchronous VLSI implementation of a CSP program, associated to a given trace of that program. This energy complexity is used in the analysis of CSP programs, in order to optimize this high level representation of asynchronous circuits for energy efficiency. A lower bound to the energy complexity of a CSP program is derived, based on the information theoretical entropy per symbol of the input/output behavior of the CSP program. This lower bound abstracts the specification of the circuit (that is, its input/output behavior), from the implementation of the specification (that is, the text of the program), and therefore applies to any program that meets the specification. A number of techniques are presented to write programs of low energy complexity, and are applied to several examples. To link the high level representat...
Supply Voltage Degradation Aware Analytical Placement
 in Proc. ACM/IEEE Intl. Conf. on ComputerAided Design, 2005
"... Increasingly significant power/ground supply voltage degradation in nanometer VLSI designs leads to system performance degradation and even malfunction. Existing techniques focus on design and optimization of power/ground supply networks. In this paper, we propose supply voltage degradation aware pl ..."
Abstract

Cited by 3 (2 self)
 Add to MetaCart
Increasingly significant power/ground supply voltage degradation in nanometer VLSI designs leads to system performance degradation and even malfunction. Existing techniques focus on design and optimization of power/ground supply networks. In this paper, we propose supply voltage degradation aware placement, e.g., to reduce maximum supply voltage degradation by relocation of supply current sources. We represent supply voltage degradation at a P/G node as a function of supply currents and effective impedances (i.e., effective resistances in DC analysis) in a P/G network, and integrate supply voltage degradation in an analytical placement objective. For scalability and efficiency improvement, we apply randomwalk, graph contraction and interpolation techniques to obtain effective resistances. Our experimental results show an average 20.9 % improvement of worstcase voltage degradation and 11.7 % improvement of average voltage degradation with only 4.3 % wirelength increase. 1
BDD decomposition for delay oriented pass transistor logic synthesis
 Very Large Scale Integration (VLSI) Systems, IEEE Transactions on Volume 13, Issue 8, Aug. 2005 Page(s):957
"... Abstract — We address the problem of synthesizing pass transistor logic (PTL), with the specific objective of delay reduction, through binary decision diagram (BDD) decomposition. The decomposition is performed by mapping the BDD to a network flow graph, and then applying the maxflow mincut techni ..."
Abstract

Cited by 3 (0 self)
 Add to MetaCart
Abstract — We address the problem of synthesizing pass transistor logic (PTL), with the specific objective of delay reduction, through binary decision diagram (BDD) decomposition. The decomposition is performed by mapping the BDD to a network flow graph, and then applying the maxflow mincut technique to bipartition the BDD optimally under a cost function that measures the delay and area of the decomposed implementations. Experimental results obtained by running our algorithm on the set of ISCAS’85 benchmarks show a 31 % improvement in delay and a 30 % improvement in area, on an average, as compared to static CMOS implementations for xor intensive circuits, while in case of arithmetic logic unit and control circuits that are nand intensive, improvements over static CMOS are small and inconsistent.
Stochastic Power/Ground Supply Voltage Prediction and Optimization via Analytical Placement
, 2007
"... Increasingly significant power/ground (P/G) supply voltage degradation in nanometer VLSI designs leads to system performance degradation and even malfunction, which requires stochastic analysis and optimization techniques. We represent the supply voltage degradation at a P/G node as a function of ..."
Abstract

Cited by 3 (0 self)
 Add to MetaCart
Increasingly significant power/ground (P/G) supply voltage degradation in nanometer VLSI designs leads to system performance degradation and even malfunction, which requires stochastic analysis and optimization techniques. We represent the supply voltage degradation at a P/G node as a function of the supply currents and the effective resistance of a P/G supply network, and propose an efficient stochastic systemlevel P/G supply voltage prediction method, which computes P/G supply network effective resistances in a random walk process. We further propose to reduce P/G supply voltage degradation via placement of supply current sources, and integrate P/G supply voltage degradation reduction with conventional placement objectives in an analytical placement framework. Our experimental results show that the proposed stochastic P/G supply network prediction method achieves 10X100X speedup compared with traditional SPICE simulation, and the proposed P/G supply voltage degradation aware placement achieves an average of 20.9 % (11.7%) reduction on maximum (average) supply voltage degradation with only 4.3 % wirelength increase.
Timingdriven Partitioning and Timing Optimization of Mixed StaticDomino Implementations
, 2000
"... Domino logic is a circuit family that is wellsuited to implementing highspeed circuits. Synthesis of domino circuits is more complex than static logic synthesis due to the noninverting nature of the logic and the complex timing relationships associated with the clockscheme. In this paper, we addre ..."
Abstract

Cited by 2 (1 self)
 Add to MetaCart
Domino logic is a circuit family that is wellsuited to implementing highspeed circuits. Synthesis of domino circuits is more complex than static logic synthesis due to the noninverting nature of the logic and the complex timing relationships associated with the clockscheme. In this paper, we address several problems along a domino synthesis ow. We mainly consider the problem of partitioning a circuit into static and domino regions under timing constraints. The algorithm is extended to develop a method for partitioning domino logic into two phases, with inverters permitted between the two phases, and then to a ow for general twophase staticdomino partitioning. We also address a timing veri cation and sizing optimization tool for circuits containing mixed domino and static logic.