In this paper, we propose the first wire density driven global routing that considers CMP variation and timing. To enable CMP awareness during global routing, we propose a compact predictive CMP model with dummy fill, and validate it with extensive industry data. While wire density has some correlation and similarity to the conventional congestion metric, they are indeed different in the global routing context. Therefore, wire density rather than congestion should be a unified metric to improve both CMP variation and timing. The proposed wire density driven global routing is implemented in a congestion-driven global router [5] for CMP and timing optimization. The new global router utilizes several novel techniques to reduce the wire density of CMP and timing hotspots. Our experimental results are very encouraging. The proposed algorithm improves CMP variation and timing by over 7 % with negligible overhead in wirelength and even slightly better routability, compared to the pure congestion-driven global router [5].

The growing packing density and power consumption of VLSI circuits have made thermal effects one of the most important concerns of VLSI designers. The increasing variability of key process parameters in nanometer CMOS technologies has resulted in larger impact of the substrate and metal line temperatures on the reliability and performance of the devices and interconnections. Recent data shows that more than 50 % of all IC failures are related to thermal issues. This article presents a brief discussion of key sources of power dissipation and their temperature relation in CMOS VLSI circuits, and techniques for full-chip temperature calculation with especial attention to its implications on the design of highperformance, low power VLSI circuits. The article is concluded with an overview of techniques to improve the full-chip thermal integrity by means of off-chip vs. on-chip and static vs. adaptive methods.

DSM and nanometer VLSI designs are subject to an increasingly significant thermal effect on VLSI circuit lifetime and performance variation, which can be effectively subdued by VLSI placement. We propose analytical placement for accurate and efficient VLSI thermal optimization, and propose minimized maximum on-chip temperature as the thermal optimization objective for improved VLSI lifetime and minimized performance variation. We develop an effective analytical thermal placement technique, as well as an improved analytical placement technique with a new cell spreading function. Our experimental results show that our proposed analytical thermal placement achieves 17.85% and 30.77 % maximum on-chip temperature variation reduction as well as 4.61 % and 0.45 % wirelength reduction respectively for the two industry design test cases compared with thermal-oblivious analytical placement, e.g., APlace. 1

This paper predicts self-heating effect in a short intrablock wire will arise as a design issue with technology scaling. The short intra-block wires are close to the substrate and thought to have good thermal radiation characteristic, however, we reveal that the self-heating of short wires will be more significantly than that of global wires, and it can cause a reliability and performance degradation in the future. The max temperature rise from the ambient temperature becomes 27.3 ◦ C in a 14 nm process. Our attribution analysis also clarifies that shrinking wire cross-sectional area as well as low-k material and increased power dissipation deteriorates self-heating. Experimental results also reveal that the self-heating of local wires will be getting worse than repeater-inserted global wires. 1.